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| author | Jim Wilson <jim.wilson@linaro.org> | 2015-06-03 00:46:19 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2015-06-02 17:46:19 -0700 |
| commit | d5726973a7a4fbeb898d9ba35235f8559295b8c7 (patch) | |
| tree | 83fcd57a10461092cab429be54c0299f02770056 /gcc | |
| parent | b20b17b1c4e71678919006a09d68418eaeb04eea (diff) | |
| download | gcc-d5726973a7a4fbeb898d9ba35235f8559295b8c7.zip gcc-d5726973a7a4fbeb898d9ba35235f8559295b8c7.tar.gz gcc-d5726973a7a4fbeb898d9ba35235f8559295b8c7.tar.bz2 | |
re PR target/66258 (compiling a stdarg function with arch +nofp generates an ICE)
gcc/
PR target/66258
* config/aarch64/aarch64.c (aarch64_function_value_regno_p): Change
!TARGET_GENERAL_REGS_ONLY to TARGET_FLOAT.
(aarch64_secondary_reload): Likewise
(aarch64_expand_builtin_va_start): Change TARGET_GENERAL_REGS_ONLY
to !TARGET_FLOAT.
(aarch64_gimplify_va_arg_expr, aarch64_setup_incoming_varargs):
Likewise.
From-SVN: r224054
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 10 |
2 files changed, 16 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d1e55c7..8d25dc9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-06-02 Jim Wilson <jim.wilson@linaro.org> + + PR target/66258 + * config/aarch64/aarch64.c (aarch64_function_value_regno_p): Change + !TARGET_GENERAL_REGS_ONLY to TARGET_FLOAT. + (aarch64_secondary_reload): Likewise + (aarch64_expand_builtin_va_start): Change TARGET_GENERAL_REGS_ONLY + to !TARGET_FLOAT. + (aarch64_gimplify_va_arg_expr, aarch64_setup_incoming_varargs): + Likewise. + 2015-06-03 Kugan Vivekanandarajah <kuganv@linaro.org> Zhenqiang Chen <zhenqiang.chen@linaro.org> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 62c8c8f..968a6b6 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1666,7 +1666,7 @@ aarch64_function_value_regno_p (const unsigned int regno) /* Up to four fp/simd registers can return a function value, e.g. a homogeneous floating-point aggregate having four members. */ if (regno >= V0_REGNUM && regno < V0_REGNUM + HA_MAX_NUM_FLDS) - return !TARGET_GENERAL_REGS_ONLY; + return TARGET_FLOAT; return false; } @@ -4783,7 +4783,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, /* A TFmode or TImode memory access should be handled via an FP_REGS because AArch64 has richer addressing modes for LDR/STR instructions than LDP/STP instructions. */ - if (!TARGET_GENERAL_REGS_ONLY && rclass == GENERAL_REGS + if (TARGET_FLOAT && rclass == GENERAL_REGS && GET_MODE_SIZE (mode) == 16 && MEM_P (x)) return FP_REGS; @@ -7571,7 +7571,7 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) vr_save_area_size = (NUM_FP_ARG_REGS - cum->aapcs_nvrn) * UNITS_PER_VREG; - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) { if (cum->aapcs_nvrn > 0) sorry ("%qs and floating point or vector arguments", @@ -7681,7 +7681,7 @@ aarch64_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, &is_ha)) { /* TYPE passed in fp/simd registers. */ - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) sorry ("%qs and floating point or vector arguments", "-mgeneral-regs-only"); @@ -7918,7 +7918,7 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode, gr_saved = NUM_ARG_REGS - local_cum.aapcs_ncrn; vr_saved = NUM_FP_ARG_REGS - local_cum.aapcs_nvrn; - if (TARGET_GENERAL_REGS_ONLY) + if (!TARGET_FLOAT) { if (local_cum.aapcs_nvrn > 0) sorry ("%qs and floating point or vector arguments", |