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| author | Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> | 2007-11-12 20:41:14 +0000 |
|---|---|---|
| committer | Dwarakanath Rajagopal <dwarak@gcc.gnu.org> | 2007-11-12 20:41:14 +0000 |
| commit | d51fba8ef2918636d8d51389297aa558b235d1ca (patch) | |
| tree | ca35a43fc303a0f7cf9ff7e3e0df391c017f8171 /gcc | |
| parent | fd0d4c1fbba96c6ddfe7377557ab8b184551cf3a (diff) | |
| download | gcc-d51fba8ef2918636d8d51389297aa558b235d1ca.zip gcc-d51fba8ef2918636d8d51389297aa558b235d1ca.tar.gz gcc-d51fba8ef2918636d8d51389297aa558b235d1ca.tar.bz2 | |
i386.md (sse5_setcc<mode>): Use <ssemodefsuffix> to get the appropriate suffix for the coms* instruction.
2007-11-12 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
Michael Meissner <michael.meissner@amd.com>
* config/i386/i386.md (sse5_setcc<mode>): Use <ssemodefsuffix>
to get the appropriate suffix for the coms* instruction.
(sse5_pcmov_<mode>): Restrict operands of pcmov
for scalar case to be only xmm registers and not memory.
* config/i386/sse.md (sse5_pcmov_<mode>): Correct the operand
constraints to follow the mnemonics for the pcmov instruction
Co-Authored-By: Michael Meissner <michael.meissner@amd.com>
From-SVN: r130120
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 13 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 14 |
3 files changed, 26 insertions, 12 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c2875f..a2da775 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2007-11-12 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + Michael Meissner <michael.meissner@amd.com> + + * config/i386/i386.md (sse5_setcc<mode>): Use <ssemodefsuffix> to + get the appropriate suffix for the coms* instruction. + (sse5_pcmov_<mode>): Restrict operands of pcmov + for scalar case to be only xmm registers and not memory. + + * config/i386/sse.md (sse5_pcmov_<mode>): Correct the operand + constraints to follow the mnemonics for the pcmov instruction + 2007-11-12 Richard Sandiford <rsandifo@nildram.co.uk> PR target/34042 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 7bc3cf4..4580afc 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14112,7 +14112,7 @@ [(match_operand:MODEF 2 "register_operand" "x") (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))] "TARGET_SSE5" - "com%Y1ss\t{%3, %2, %0|%0, %2, %3}" + "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "sse4arg") (set_attr "mode" "<MODE>")]) @@ -19738,13 +19738,16 @@ [(set_attr "type" "fcmov") (set_attr "mode" "XF")]) +;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict +;; the scalar versions to have only XMM registers as operands. + ;; SSE5 conditional move (define_insn "*sse5_pcmov_<mode>" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,x,x") + [(set (match_operand:MODEF 0 "register_operand" "=x,x") (if_then_else:MODEF - (match_operand:MODEF 1 "nonimmediate_operand" "xm,x,0,0") - (match_operand:MODEF 2 "nonimmediate_operand" "0,0,x,xm") - (match_operand:MODEF 3 "vector_move_operand" "x,xm,xm,x")))] + (match_operand:MODEF 1 "register_operand" "x,0") + (match_operand:MODEF 2 "register_operand" "0,x") + (match_operand:MODEF 3 "register_operand" "x,x")))] "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)" "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}" [(set_attr "type" "sse4arg")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b35ba6f..9cf5555 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -7894,15 +7894,15 @@ (define_insn "sse5_pcmov_<mode>" [(set (match_operand:SSEMODE 0 "register_operand" "=x,x,x,x,x,x") (if_then_else:SSEMODE - (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,xm,0,0") - (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,x,C,x") - (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,0,x,C")))] + (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,x,0,0") + (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,0,C,x") + (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,xm,x,C")))] "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)" "@ - pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0} - pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0} - pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0} - pcmov\t{%3, %2, %1, %0|%3, %1, %2, %0} + pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3} + pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3} + pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3} + pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3} andps\t{%2, %0|%0, %2} andnps\t{%1, %0|%0, %1}" [(set_attr "type" "sse4arg")]) |