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| author | Jan Beulich <jbeulich@novell.com> | 2005-01-11 08:57:24 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@gcc.gnu.org> | 2005-01-11 08:57:24 +0000 |
| commit | d3f6e07b9a129f1f090e4290c54448cacc0e0eb1 (patch) | |
| tree | aad1291a450f97a162364c0fcab22912ff8800e0 /gcc | |
| parent | 201dd46b9827597fdc60534fd9de31f36f998be3 (diff) | |
| download | gcc-d3f6e07b9a129f1f090e4290c54448cacc0e0eb1.zip gcc-d3f6e07b9a129f1f090e4290c54448cacc0e0eb1.tar.gz gcc-d3f6e07b9a129f1f090e4290c54448cacc0e0eb1.tar.bz2 | |
ia64.md (zero_extendsidi2): Replace zxt4 by addp4.
gcc/
2005-01-11 Jan Beulich <jbeulich@novell.com>
* config/ia64/ia64.md (zero_extendsidi2): Replace zxt4 by addp4.
Change respective itanium_class attribute to ialu.
(shladdp4_internal): New.
* config/ia64/predicates.md (shladd_log2_operand): New.
From-SVN: r93178
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.md | 13 | ||||
| -rw-r--r-- | gcc/config/ia64/predicates.md | 5 |
3 files changed, 22 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a9d0155..a525f32 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-01-11 Jan Beulich <jbeulich@novell.com> + * config/ia64/ia64.md (zero_extendsidi2): Replace zxt4 by addp4. + Change respective itanium_class attribute to ialu. + (shladdp4_internal): New. + * config/ia64/predicates.md (shladd_log2_operand): New. + 2005-01-11 Richard Henderson <rth@redhat.com> * expr.c (store_constructor): Use rtvec_alloc instead of diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 8ce878d..a41398d1 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -866,10 +866,10 @@ (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] "" "@ - zxt4 %0 = %1 + addp4 %0 = %1, r0 ld4%O1 %0 = %1%P1 fmix.r %0 = f0, %1" - [(set_attr "itanium_class" "xtd,ld,fmisc")]) + [(set_attr "itanium_class" "ialu,ld,fmisc")]) ;; Convert between floating point types of different sizes. @@ -1138,6 +1138,15 @@ [(set_attr "itanium_class" "ishf")]) ;; Combine doesn't like to create bit-field insertions into zero. +(define_insn "*shladdp4_internal" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") + (match_operand:DI 2 "shladd_log2_operand" "n")) + (match_operand:DI 3 "const_int_operand" "n")))] + "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" + "shladdp4 %0 = %1, %2, r0" + [(set_attr "itanium_class" "ialu")]) + (define_insn "*depz_internal" [(set (match_operand:DI 0 "gr_register_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md index 7c9a76f..fc94d82 100644 --- a/gcc/config/ia64/predicates.md +++ b/gcc/config/ia64/predicates.md @@ -312,6 +312,11 @@ (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8 || INTVAL (op) == 16"))) +;; True if OP is one of the immediate values 1, 2, 3, or 4. +(define_predicate "shladd_log2_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 1 && INTVAL (op) <= 4"))) + ;; True if OP is one of the immediate values -16, -8, -4, -1, 1, 4, 8, 16. (define_predicate "fetchadd_operand" (and (match_code "const_int") |