RISC-V: Introduce option -mrvv-max-lmul for RVV autovec

Following replacement of -param=riscv-autovec-preference with -mrvv-vector-bits, this patch replaces -param=riscv-autovec-lmul with -mrvv-max-lmul. -param issue is mentioned in following links: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651 Tested On RV64 and RV32, no regression. PR target/112651 gcc/ChangeLog: * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename (enum rvv_max_lmul_enum): Ditto (TARGET_MAX_LMUL): Ditto * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto (costs::better_main_loop_than_p): Ditto * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/autovec/bug-2.C: Replace option * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr111317.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr111848.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/pr114264.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c: Ditto * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: Ditto * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: Ditto * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: Ditto * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: Ditto * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Ditto * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Ditto * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Ditto * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Ditto * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Ditto * gcc.target/riscv/rvv/autovec/pr112450.c: Ditto * gcc.target/riscv/rvv/autovec/pr112598-1.c: Ditto * gcc.target/riscv/rvv/autovec/pr112598-2.c: Ditto * gcc.target/riscv/rvv/autovec/pr112694-1.c: Ditto * gcc.target/riscv/rvv/autovec/pr112999.c: Ditto * gcc.target/riscv/rvv/autovec/pr113393-2.c: Ditto * gcc.target/riscv/rvv/autovec/series-1.c: Ditto * gcc.target/riscv/rvv/autovec/series_run-1.c: Ditto * gcc.target/riscv/rvv/autovec/slp-interleave-1.c: Ditto * gcc.target/riscv/rvv/autovec/slp-interleave-2.c: Ditto * gcc.target/riscv/rvv/autovec/slp-interleave-3.c: Ditto * gcc.target/riscv/rvv/autovec/slp-interleave-4.c: Ditto * gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/abs-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/and-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/and-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/and-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/avg-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/bswap16-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cmp-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/compress-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_add-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_add-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_and-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_div-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_div-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_max-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_max-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_min-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_min-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_not-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/consecutive-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/consecutive-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/const-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/const-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/const-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/const-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/const-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/convert-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/cvt-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/div-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/dup-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ext-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ext-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ext-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ext-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ext-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/extract-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/extract-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fma-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fms-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fms-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnma-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnms-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/fnms-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ior-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ior-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/ior-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mask-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mask-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mask-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-floor-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-irint-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-irint-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-iround-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-iround-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llround-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lround-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lround-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-rint-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-round-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/max-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/merge-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/min-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/minus-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/minus-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/minus-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-13.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-14.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-15.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-16.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-17.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mulh-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/mult-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/narrow-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/narrow-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/narrow-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/neg-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/neg-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/not-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/perm-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/plus-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/plus-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/plus-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-13.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-14.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-15.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-16.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-17.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-18.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-19.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-20.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-21.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/reduc-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/repeat-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/series-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/series-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/series-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/series-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/shift-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/spill-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/spill-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/spill-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/spill-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/spill-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/sqrt-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trailing-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trunc-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trunc-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trunc-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trunc-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/trunc-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: Ditto * gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wadd-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wadd-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wadd-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wadd-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfma-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfma-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfnma-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wfnms-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wmul-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wmul-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wmul-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wred-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wred-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wred-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wsub-1.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wsub-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wsub-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/wsub-4.c: Ditto * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Ditto * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Ditto * gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto * gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto * gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto * gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto * gcc.target/riscv/rvv/base/cpymem-1.c: Ditto * gcc.target/riscv/rvv/base/cpymem-2.c: Ditto * gcc.target/riscv/rvv/rvv.exp: Ditto * gcc.target/riscv/rvv/vsetvl/pr111255.c: Ditto * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Ditto * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Ditto Signed-off-by: demin.han <demin.han@starfivetech.com>
author: demin.han <demin.han@starfivetech.com> 2024-03-13 18:43:26 +0800
committer: demin.han <demin.han@starfivetech.com> 2024-03-20 16:38:10 +0800
commit: cd1ce3b326d49c16bade1fb76daa2ee67586efc9 (patch)
tree: 4414dfaae2c2230e164b8300cfe018823125653f /gcc
parent: 6a55e39bdb1fdb570730c08413ebbe744e493411 (diff)
download: gcc-cd1ce3b326d49c16bade1fb76daa2ee67586efc9.zip
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gcc-cd1ce3b326d49c16bade1fb76daa2ee67586efc9.tar.bz2
547 files changed, 612 insertions, 612 deletions
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 9ae86d5..392b916 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -74,7 +74,7 @@ enum stack_protector_guard {
 };
 
 /* RISC-V auto-vectorization RVV LMUL.  */
-enum riscv_autovec_lmul_enum {
+enum rvv_max_lmul_enum {
   RVV_M1 = 1,
   RVV_M2 = 2,
   RVV_M4 = 4,
@@ -152,6 +152,6 @@ enum rvv_vector_bits_enum {
 
 /* The maximmum LMUL according to user configuration.  */
 #define TARGET_MAX_LMUL                                                        \
-  (int) (riscv_autovec_lmul == RVV_DYNAMIC ? RVV_M8 : riscv_autovec_lmul)
+  (int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)
 
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 967f4e3..814c5fe 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2338,7 +2338,7 @@ preferred_simd_mode (scalar_mode mode)
   if (autovec_use_vlmax_p ())
     {
       /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
-	 riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
+	 rvv_max_lmul as multiply factor to calculate the NUNITS to
 	 get the auto-vectorization mode.  */
       poly_uint64 nunits;
       poly_uint64 vector_size = BYTES_PER_RISCV_VECTOR * TARGET_MAX_LMUL;
diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc
index 5ac8655..f462c27 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -890,7 +890,7 @@ costs::record_potential_unexpected_spills (loop_vec_info loop_vinfo)
 {
   /* We only want to apply the heuristic if LOOP_VINFO is being
      vectorized for VLA and known NITERS VLS loop.  */
-  if (riscv_autovec_lmul == RVV_DYNAMIC
+  if (rvv_max_lmul == RVV_DYNAMIC
       && (m_cost_type == VLA_VECTOR_COST
 	  || (m_cost_type == VLS_VECTOR_COST
 	      && LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo))))
@@ -998,7 +998,7 @@ costs::better_main_loop_than_p (const vector_costs *uncast_other) const
 	  return other_prefer_unrolled;
 	}
     }
-  else if (riscv_autovec_lmul == RVV_DYNAMIC)
+  else if (rvv_max_lmul == RVV_DYNAMIC)
     {
       if (other->m_has_unexpected_spills_p)
 	{
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 710c0a4..7d625af 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -531,27 +531,27 @@ Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64)
 Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64).
 
 Enum
-Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum)
-The RVV possible LMUL (-param=riscv-autovec-lmul=):
+Name(rvv_max_lmul) Type(enum rvv_max_lmul_enum)
+The RVV possible LMUL (-mrvv-max-lmul=):
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m1) Value(RVV_M1)
+Enum(rvv_max_lmul) String(m1) Value(RVV_M1)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m2) Value(RVV_M2)
+Enum(rvv_max_lmul) String(m2) Value(RVV_M2)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m4) Value(RVV_M4)
+Enum(rvv_max_lmul) String(m4) Value(RVV_M4)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(m8) Value(RVV_M8)
+Enum(rvv_max_lmul) String(m8) Value(RVV_M8)
 
 EnumValue
-Enum(riscv_autovec_lmul) String(dynamic) Value(RVV_DYNAMIC)
+Enum(rvv_max_lmul) String(dynamic) Value(RVV_DYNAMIC)
 
--param=riscv-autovec-lmul=
-Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) Init(RVV_M1)
--param=riscv-autovec-lmul=<string>	Set the RVV LMUL of auto-vectorization in the RISC-V port.
+mrvv-max-lmul=
+Target RejectNegative Joined Enum(rvv_max_lmul) Var(rvv_max_lmul) Init(RVV_M1)
+-mrvv-max-lmul=<string>	Set the RVV LMUL of auto-vectorization.
 
 madjust-lmul-cost
 Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
index 53bc4a3..1234ae4 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/autovec/bug-2.C
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-max-lmul=m4" } */
 
 int max(int __b) {
   if (0 < __b)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
index 4f019cc..9e83a24 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 int a, *b[9], c, d, e; 
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
index 6fc8062..cd354d7 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -Ofast -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 typedef struct rtx_def *rtx;
 struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
index c1f698b..c0a7e1c 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto -fno-use-linker-plugin -flto-partition=none --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto -fno-use-linker-plugin -flto-partition=none -mrvv-max-lmul=dynamic" } */
 
 void (*foo[6][6]) (int);
 void bar (hdR)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
index e654fc6..8d00028 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-mixed-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
index f481c80..d5fd0f2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
index e044c65..a0e6130 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fno-schedule-insns -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fno-schedule-insns -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
index 212788a..2111c0b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
index 2e2ff9d..c47a4c4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
index 80eb38c..e4b74f0 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
index 3dd594e..73d16da 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-6.c
@@ -1,6 +1,6 @@
 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
index a8c98c4..b76bb4b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
index 0079aa0..6637f3c 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
index d8a0e66..5545122 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
index 0079aa0..6637f3c 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
index 2326919..a8e603f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
index 2ef88a3..dcb20a3 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 typedef int8_t v128qi __attribute__ ((vector_size (128)));
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
index 5eec2b0..f5d1a02 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 typedef int8_t v128qi __attribute__ ((vector_size (128)));
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
index 38cbefb..49ea3c2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 int
 x264_pixel_8x8 (unsigned char *pix1, unsigned char *pix2, int i_stride_pix2)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
index 08dc7ca..6508213 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
index e47af25..4a372ed 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 int
 bar (int *x, int a, int b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
index 48b2427..0f0cd59 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c, int *__restrict d,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
index 0cb492e..29e6dfc 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
index b9a9229..95742e2 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
index 9af91b0..85e3021 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
index 2a881da..c4cb208 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
index b23aceb..3734b5c 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
index 45bceaa..1d37a51 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
index ef719ee..756176d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
index 7fda83a..46450f4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fselective-scheduling -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
index 702a3b7..87e6b09 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
index 95b0600..bd5aa80 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
index 83df2bc..c9e2825 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
index 8a2ebf5..9fa6b69 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */
 
 void
 foo (int *restrict a, int *restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
index baef4e3..40a3acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
index 0d42c3b..9a9bb48 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 void
 f (int *restrict a, int *restrict b, int *restrict c, int *restrict d, int x,
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
index c3d0d5d..15c615f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
index a575427..c0f55a4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
index b55bcad..91af60d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 #include <stddef.h>
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
index 307dd69..ba2822f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
index 9a7eb42..d8c3653 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
index 103d22b..33012ec 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
index 0255bdf..aad04c4 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
index e6cc1ad..f045f85 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
index 6752f25..2e7baa3 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/no-dynamic-lmul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
index d4bea24..8b4d972 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111317.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m1" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m1" } */
 
 void
 foo (char *__restrict a, short *__restrict b, int n)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
index 5a673f5..339c80f 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr111848.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
 
 #include <stdint-gcc.h>
 void
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
index 6d8a1d4..7f97c42 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define N 40
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
index 9401e39..fd27b29 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */
 
 #define TYPE double
 #define N 200
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
index 07e0cdf..86241e7 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 int f[12][100];
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
index 215f6de..a7ee7b0 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct rtx_def *rtx;
 struct replacement {
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
index 9ab2ab9..263d41b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */
 
 typedef struct {
   int iatom[3];
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
index 0d09a62..0c76bcc 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
index af3712c..309dcf7 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic -mrvv-vector-bits=zvl" } */
 
 #include "pr113247-1.c"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
index 706e191..d8402dc 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m8" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
index 3947a9a..a5319e9 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
index d3f5717b..0163129 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 unsigned char a;
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
index 7853f29..e51d80e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114264.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-max-lmul=dynamic" } */
 
 char *jpeg_difference7_input_buf;
 void
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
index 89a6c67..1444793 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
index 86732ef..13ae8bd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
index a1fcb3f..1f9fa48 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
index ca203f5..4a979df 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
index f8e5335..d48375b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m4" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
index 4859d57..36dc0ad 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
index 8a56802..993fae0 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
index 46ebd5f..7fd8397 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
index f5aceca..1519a0d 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic" } */
 
 void
 foo (int *__restrict a, int *__restrict b, int *__restrict c)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
index 7f03cb9..cb4abec 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
index 86ad19c..5222b1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl  -fno-vect-cost-model -O3 -fdump-tree-optimized" } */
 
 #include <assert.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
index 07f9d91..a6dbbaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-require-effective-target riscv_v } */
-/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
+/* { dg-options "-mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */
 
 #define N 128 
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
index 9af5add..05ac2e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */
 
 #define N 16
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
index 1b6ad26..a2e353b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 typedef struct {
   short a;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
index 1a3fc16..cff18b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-max-lmul=m4 -mrvv-vector-bits=zvl" } */
 
 typedef unsigned char u8;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
index 91fc5dd..6009a51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 -mrvv-max-lmul=m2 -mrvv-vector-bits=zvl" } */
 
 union U
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
index c900327..54ad8c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
index 544ff75..033ed10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
index 63ded00..b38afaf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
index f29b5f1..54ebcdf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-lmul=dynamic -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=dynamic -fdump-tree-optimized-details" } */
 
 #include "macro.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
index a80c3b9..034b121 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
index c2a207d..ac3e439 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
index 9dbecee..610b6ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
index 7c31901..887c1c2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 
 #include "cond_widen_reduc-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
index 85917fe..cd3b95fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */
+/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1" } */
 
 void foo1 (int* restrict a, int* restrict b, int n)
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
index cf6d742..297ffdb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
index ce50d80..a96e6ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns -mrvv-max-lmul=m1 -O3 -ftree-vectorize" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include <stdint-gcc.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
index fae1ab5..a4424f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c
@@ -20,7 +20,7 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvand} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
index 02fb365..1c7503b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c
@@ -20,7 +20,7 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1"} } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1"} } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
index 3adec12..0da6658 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c
@@ -30,7 +30,7 @@ f (uint8_t *restrict a, uint8_t *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
index 8f1a7e1..cedd3f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c
@@ -22,7 +22,7 @@ f (float *restrict a, float *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1 or m2.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 2 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
index 2fa6168..d386c4f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c
@@ -22,7 +22,7 @@ f (float *restrict a, float *restrict b,
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1 or m2.  */
-/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
-/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "--param riscv-autovec-lmul=m1" "--param riscv-autovec-lmul=m2" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1 or m2.  */
+/* { dg-final { scan-tree-dump "\.VEC_PERM" "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
+/* { dg-final { scan-assembler {\tvid\.v} { xfail { any-opts "-mrvv-max-lmul=m1" "-mrvv-max-lmul=m2" } } } } */
 /* { dg-final { scan-assembler-not {\tvmul} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
index 08ac776..68991a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c
@@ -20,5 +20,5 @@ f (int16_t *restrict a, int16_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
index 88598e6..35659d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c
@@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
index 7543eca..2ab3846 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c
@@ -20,5 +20,5 @@ f (int16_t *restrict a, int16_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
index eaa580f..a10a7c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c
@@ -20,5 +20,5 @@ f (int8_t *restrict a, int8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
index 324cae0..395f902 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c
@@ -20,6 +20,6 @@ f (uint8_t *restrict a, uint8_t *restrict b, int n)
 }
 
 /* FIXME: Since we don't have VECT cost model yet, LOAD_LANES/STORE_LANES are chosen
-   instead of SLP when riscv-autovec-lmul=m1.  */
-/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "--param riscv-autovec-lmul=m1" } } } } */
+   instead of SLP when rvv-autotec-max-lmul=m1.  */
+/* { dg-final { scan-tree-dump-times "\.VEC_PERM" 1 "optimized" { xfail { any-opts "-mrvv-max-lmul=m1" } } } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
index 964a4d3..ec118b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112450.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 --param=riscv-autovec-lmul=m8 -fno-vect-cost-model" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -mrvv-max-lmul=m8 -fno-vect-cost-model" } */
 
 int a, b, d, e;
 short c;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
index a1d7e5b..e962ca1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -O3 -fno-vect-cost-model -ffast-math" } */
+/* { dg-options "-march=rv32gcv_zvfh_zfh_zvl512b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -O3 -fno-vect-cost-model -ffast-math" } */
 
 #include <stdint-gcc.h>
 #define TEST_UNARY_CALL_CVT(TYPE_IN, TYPE_OUT, CALL) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
index d32e8ba..53abe09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112598-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
index 3743ac8..6b3b7a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
+/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 -mrvv-max-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
index a1244c1..2c63ee5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */
 
 int a[1024];
 int b[1024];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
index 2d203ea..8f25157 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */
+/* { dg-options "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" } */
 /* { dg-require-effective-target riscv_v } */
 
 __attribute__((noinline, noclone)) static int
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
index 43da34e..a88f602 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
index b318364..8c50f85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } */
 
 #include "series-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
index 9f37143..296fd4a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
index 6cc390c..d992c4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
index 326d66e..96bd8ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
index 2bb73eb..64483c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zve32f_zvl1024b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gc_zve32f_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
 
 struct S { int a, b; } s[8];
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
index 5fb61c7..080c02c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-lroundf16-rv64-ice-1.c
@@ -1,6 +1,6 @@
 /* Test that we do not have ice when compile */
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-mrvv-max-lmul=m4 -march=rv64gcv_zvfh_zfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "test-math.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
index f1600e0..36ca75e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m2" } */
 #include <stdint-gcc.h>
 #include <assert.h>
 #define N 16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
index c41f11b..ddad6f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m2" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
index 12174f7..85f044e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m4" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
index 7ecfc80..9ad5011 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
index 3554b6c..3424d91 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
index 0957abd..2f64aac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
index 4f265d3..0162d8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
index 32bbea7..4b27a57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
index 85ab1ee..51d0354 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */
+/* { dg-options "-mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -O3" } */
 
 #include <stdint-gcc.h>
 #include <assert.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
index 89c1af3..4bc6f76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
index d84c21d..e08a93c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
index 0a0d9b2..92d1a06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include "trailing-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
index 194d18b..d25ed77 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c
@@ -1,5 +1,5 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-mrvv-vector-bits=zvl -O3 -mrvv-max-lmul=m8" } */
 
 #include "trailing-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
index 7c7a5bd..6584030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
index e98f5c4..5389a55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
index 15ffdf6..2cfef6d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
index d0e68b1..ad8c8f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
index 5b697dd..ceb806f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
index 2327a3d..30e60d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
index 8030810..33df429 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
index dce0ffa..9058905 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
index 65912fb..8d106aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
index a197b24..981abd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
index a53de71..bfe4ba3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
index 11880ba..0707277 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/bswap16-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
index 05742b9..965cb1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
index 39a5602..eda6070 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
index 387157d..fba1056 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
index 40b8871..7731070 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
index 378b704..d01153d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
index f0351e0..264520f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
index 7afb194..edabcde 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
index cbb5995..f9560f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
index abd49c0..8cf237f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
index 6fa9b13..996bb743 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
index 2a87932..34df94c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
index 88bfe58..e024001 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
index eeb9690..6f42922 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
index 4622a5b..b05eb12 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
index 0d4776c..c06c8ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
index 4af45cc..02f0a5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
index d2f1852..9393836 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
index ae6e712..7d7221d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
index f8d5e40..9920d0f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
index 3eaf8bb..b2e52b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
index 52fd64d..e3f31b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
index af6aaf3..394a263 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
index a1dacac..29e020b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
index 99d4019..7de13fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
index 5165d47..e84e5b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
index d270dd9..1cc0100 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
index ea77cb0..f2e3941 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
index 537a032..0a3a0b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
index e643147..fee8428 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
index 5e87294..fc883a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
index a4ceb62..31bdd97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
index f407027..c1ab0fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
index ffc0b8f..56e7758 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/compress-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/compress-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
index 3eaabce..2f6de61 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
index 61da94c..06a62e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
index cb73087..fb53738 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_add-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
index eb8d56a..01ff61c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_and-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
index 3baf5cf..59c2f8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
index e56dc33..3eebcd0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
index 41ec468..2a9a9ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
index c2cb8bfd..4444ad8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
index beecdf4..79b8325 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
index f71236b..d2b6291 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
index fa5780c..cdadf5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
index 696e17c..d061aa7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
index a830777..4394233 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
index 6f56cb6..881bd57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
index 62cc7a3..f439806 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
index 14ae1a3..47fd131 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_convert-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
index 5519158..e99a702 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_copysign-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
index 373ff00..4c6a21b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
index fac75ef..894e839 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_div-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
index c356cf5..73f425e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
index 02bdf65..d714f3f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
index 2db3ea2..9c3790c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
index 192722c..98a5eb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
index 96ba993..3f3882a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ext-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
index 54d2f07..939c87d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
index 145f81f..5d69285 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
index bfed1db..5f00d51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
index 5871c71..12bcafb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
index f91039a..9375c84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
index 59fae9b..a8f8890 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_fnms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
index 2c30854..d8e5350 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_ior-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
index 60e0f93..1b59686 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
index f8db292..f46298c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_max-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
index 2a13c25..760c6f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
index 0ae8208..9556006 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_min-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
index 060c58b..4d9862d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mod-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
index f6b58c1..8e8cf99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
index 4df3d55..36a7266 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mul-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
index ffa6458..f92cecc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_mulh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
index 08f2285..a947a08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
index 41452e7..2f220c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_narrow-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
index ca94446..1da9312 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
index cf44c18..bbe734c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_neg-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
index 1a2a8f4..3096095 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_not-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
index 3ac6203..3e94dbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
index 8c2fa47..e9d4e37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_shift-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
index 1c1c2ab..283f2d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
index 629e66c..8ef4575 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
index 385ab41..a7c9760 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sub-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
index f548856a..dce94c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
index 5d38c77..2a0d8bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
index 7596733..510c656 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
index 867de13..d2b8ece 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
index 12ca119..72a5147 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_trunc-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
index ccaaf31..218a475 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
index d2a67c8..c7132e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
index 6ae95f3..9814e8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
index d9056e6..d28242d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wadd-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
index fa4022b..4eece1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
index 5a2bfed..34b9f02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
index 86fbe0b..ce7c1c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
index fa0fc64..79ec5af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wfnma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
index f18cd66..ae5bddc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
index b7a6d52..af9e20a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
index 64ca747..17c9a58 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wmul-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
index 887aabd..7dd2987 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
index 4093450..9fd3471 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
index 20e3a8f..d9eae4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
index b97cd8a..b0cb287 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_wsub-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
index 1bb0570..b6b0007 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_xor-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
index b9bc15f..f9a763a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
index 8c0bc20..8f5103c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/consecutive-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
index f3217e6..2ff2cf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
index 99255ec..c827f3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
index a9c8ae3..a9f531c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
index 50d1515..f95be04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
index afc2a87..21ab91c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/const-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
index ca04f7f..99004c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
index 95d04cd..8abbe59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
index 853acb3..9f96da75 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
index 8fdfa44..858c915 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
index 4b6a168..3c0106d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
index 6d74bdd..e4237ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
index 8ef991d..3fea034 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
index 09a44de..2381284 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
index 2948dde..6db4406 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
index ea39012..f486337 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
index 59f36f5..d895d8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
index 3546ddc..9f0da2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/convert-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-trapping-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
index 5637b05..6083aff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cvt-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -ffast-math --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -ffast-math -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
index 7d8a3e2..1b9e058 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
index 1f520f2..9952861 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
index 1a930d0..fdd335f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
index 46fb5a5..f95e8b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
index 7e46dc4..74625b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
index 9b9327b..511f3ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
index 52d5a65..41616e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
index 39f27ec..6e18304 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/dup-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-builtin -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
index e46990e..151d0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
index 03968a6..0879f5a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
index 4cc1930..f8c9cf4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
index 7593a35..23fa14b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
index 5dca5a7..9dd20a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
index 907a708..f593daf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
index 7daa074..48ef9f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/extract-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
index 5c2da4d..382860b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
index 73a355b..042dd0d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
index 42925e5..fffaa123 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
index 93a9e39..89a9e56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
index a5bc2a0..1a3aff7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
index f1fb7ed..19b5ba5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
index 8d3cd2a..ef625d5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
index a13de04..8dc5a31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
index 108a883..6f31e27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
index d748018..db3bf86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
index dd16368..231919e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
index e082c47..4706268 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
index 1b90052..101ad57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
index ad05800..65afa96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
index 5d4109a..004a95c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
index 0e3cbf2..82a8696 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
index 3beccb2..5464c80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
index b961638..297f049 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
index d8e4e26..f49bf28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
index 0cc18d9..fa89c52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
index 3a66481..518bebb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
index 86c23ef..9ca1365 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
index ec9001f..2190313 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -ffast-math" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
index 75fe340..12bbbc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
index 96a6fe6..8ddefc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
index 0094e2c..54a3adf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
index 7f9073a..ce8f351 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
index ddc4b55..94b2327 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
index 3bb52ae..24842f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
index 903a4f7..01ebc8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
index de565b76..ad97a08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
index 97fd9b8..8a61d24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
index c6dc9f7..6f806b8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fma-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
index 491ed00..37150e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
index ade6cb1..28dc7ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
index 1746f17..203eebf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fms-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
index 418c767..f10d1f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
index c1b629a..ae96bac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
index bab693e..babe296 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
index f0a7c5d..3cdfff6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
index 053f1ee..72ffdd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
index 9053517..b57d842 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
index 9952a49..0b3e195 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnma-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
index 7fb8884..162f3e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
index b044061..13f1dfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
index 5547bc4..bb4a403 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/fnms-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
index 0f78ae0..f16f709 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
index ae31e22..fbe6ce8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
index df15bd7..189423c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl256b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
index 09bdbd1..145e7d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
index 65ca8cb..3081e16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl512b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
index 9cd36ce..6af57b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
index ad33705..c11ce43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl1024b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
index 9bb21d7..5549f87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
index e5934ac..1b2d1de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
index 7b30e2b..428bb4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
index d3efc9a..38a8784 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
index a9d1e87..7f21a36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
index b528c80..b92d558 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
index 5c36d86..8517078 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
index 1087b60..4fa651a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
index f0d40df..0b339d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
index dcee81a..ce67471 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
index adcba29..c07fd20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
index ed142d5..cc0c19a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
index d5b65ff..bfa226b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
index 7fe4ec9..4a78163 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
index 7d2254b..bb31a5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
index b113df8..c35c6f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ceil-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
index 076580e..aa69d69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-floor-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
index f8877a1..b14cc5d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
index a2a2e24..8c0b444 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
index 69eaa11..de145f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
index b6a2122..1dbf472 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-ifloor-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
index 3297bc6..b2ce700 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
index 5447326..31436a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-irint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
index 12fe7a2..8e8feeb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
index bad232d..e5b95db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iround-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
index f843574..ffef193 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
index 2d40808..c29ae88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
index 94168c1..d9b0848 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceil-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
index 12ac4e5..2ea751e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lceilf-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
index fe61e99..347cb07 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
index a64e5c4..4d8caf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
index f5a8311..30aa13d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloor-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
index 08b1b7f..c170a87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lfloorf-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
index 204e3ad..919ce1e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceil-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
index 09842c0..710400f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llceilf-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
index 205a5d2..f3ffa0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloor-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
index b72eaf9..3dadab1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llfloorf-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
index b0bf422..ada0b98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrint-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
index 9445f5d..07ead40 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
index be2373d..622b9bf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llrintf16-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
index 9bed764..c195e27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llround-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
index d3993fc..60c670a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
index 0ca112d..860af08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-llroundf16-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
index 561edef..d768dce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
index 5414352..cfbd063 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
index 61563e4..0126831 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
index b095ff2..11c62f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
index f78c8e3..78f5df4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
index 21ef441..37de334 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lrintf16-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
index c2a9f6b..0ae48d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
index 5a43133..c9e29a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32f -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
index f526854..a915971 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lround-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
index 2c6515a..3942969 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
index 4b66070..7080927 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv32-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
index 9fa4563..3d8967d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-lroundf16-rv64-0.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
index 8c8498c..bb62ce2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-nearbyint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
index cf10d61..9896e30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
index 97fd697..33806f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-round-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
index 8489d39..fe5b289 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-roundeven-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
index 51211bd..d1c080ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-trunc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
index e4400c2..c98357f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
index 9cbc845..cd24922 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
index e270db9..52d9124 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
index 033952f..4931d2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
index 62ed1a5..f22a18f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
index 42fa2ec..cf8d04c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
index d5222f6..3b6f977 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
index bd097f0..b025713 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/merge-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
index 41e2d26..42b8d8c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
index 4d698ba..10aacf3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
index 2d9dd62..10f9a7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
index 2625c16..4dff0aa2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
index 6e08f77..1a076cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/misalign-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m4 -fno-tree-loop-distribute-patterns" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m4 -fno-tree-loop-distribute-patterns" } */
 
 #include <stdlib.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
index 17d2784..4bb94be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
index 18dad34..bd34f02 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
index c199c33..0de41d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
index 4737008..81720db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
index f61c372..eae2bdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
index 56a7cf0..736f04f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
index de49ed8..4606484 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
index bed6a47..5c0795d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
index 06ab31b..871225a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
index c2f0e3c..c0d0ae5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
index 77d3fed..ca33224 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
index 5fae343..0f331e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
index c515f02..175bbb5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
index 1164ab5..76b81ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
index 404ef5d..73be9d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "def.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
index 47bb40f..fe1dd7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mulh-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
index 0d1b5a4..58bb428 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
index ca6b856..a419de6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
index 3838ee5..f87f5ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
index 03d03dc..26ea118 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/narrow-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
index 0d723d7..fb58d2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
index c2ab009..a980364 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
index 316bac8..3cdeed0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/not-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
index 327913b..35a648b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-1.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
index d562312..2379976 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
index 87319e3..0d407efc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-3.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
index 4d6862c..a970631 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-4.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
index 3460315..b465d55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-5.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
index a2a722f..e20964b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-6.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
index b474ccf..6cc753f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/perm-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "../vls-vlmax/perm-7.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
index 146b4dd..6b19f2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
index 6ce0719..797e7b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
index c68b2bc..d32d9d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
index b6d8e6a..fb7dfb8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
index 22aace4..b5187e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
index 0e8518a..6ad0207 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
index aabbe71..3fc84c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
index c3f5f2c..ab548f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
index 61eea79..12baca0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
index a368e55..0db6e67 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
index c528d69..d856bf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
index d0f00e6..e208a4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
index ba8fb52..24a9a6bf9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
index 5130fe5..5a4df48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
index 158aaf3..3d84592 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
index 819104a..daf9c8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
index 2b61e0a..d1b8c25 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
index d24f2ef..18436aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
index 1143bde..f34ee84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
index 0370b4d..bcfc536 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
index 954e39d..52f7284 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
index 6762db8..faae666 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
index 905c9d0..a7e02d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
index be7c323..7d63738 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized-details" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized-details" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
index 2c831f9..3fe720d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
index a465bb6..e9102d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
index 9c9899b..e02f6fc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
index 17bc313..f552439 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
index 6398f24..1de2d43 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
index 960a164..11b1486 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
index 98be878..4ba0f85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
index b8d952e..441d801 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
index 1db68fc..7331ad0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/repeat-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
index b575bb9..d515887 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
index c84eed1..9c4381d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
index 16cce76..6d56974 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
index 966391e..1a07f8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/series-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fno-builtin" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8 -fno-builtin" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
index ee8da25..eb3f32c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
index ebd5575..8caed20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
index 244bee0..f54cb09 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
index 56b6ef9..ee80ffd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
index c909cb1..ee09780 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
index fdea84c..07cfcff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
index 842bb63..b64c73f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
index 8f6ee81..8fcdca7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
index 0f317d6..ca296ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
index b366a46..150135a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
index d35e2a4..c5d2d019 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param=riscv-autovec-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
index 60dbfd7..1d94d57 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/sqrt-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
index ed15a12..675ce85 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
index 5deb097..475dcf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
index e503d6c..974d566 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
index c794564..19170a5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
index 43e1792..a479745 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
index bb91c6a..17ec6d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
index b12f08d..21e2c10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trailing-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
index ae129d0..c197db3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
index 0631dad..25bb2a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
index 3c5f045..1993c63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
index d9a5eeb..bd931e8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
index b87a5c4..41d2ce4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
index d53fdc2..3640b6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
index c924236..a0f02c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
index 4ec8678..c3b20c4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
index 4436830..3da7fa1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
index 037a4a6..230d431 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
index 4dd5888..0379fa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
index 77eeed4..fcc80cf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
index 4f2bb2c..105cb96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
index 9376aee..3a75926 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
index ade887e..aa7aea8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
index 7106bd9..efbe874 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
index 6132bb4..68e3c9d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
index 2da3e3c..88f2769 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
index db2682a..a483304 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
index 3bb3936..f100e5f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
index 6080060..42080e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
index 09852f7..474057e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
index b6a4d1a..6864d7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
index 11e22db..b8cdc08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
index d4ce093..58e3e7d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
index 4beb2b0..8292ee9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
index b59f3f3..ae45b71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -mrvv-max-lmul=m8" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
index bce56b7..2269a4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
index d0b55c0..b4ab497 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
index b6067c8..dbae1f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
index 253750a..21c29bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wadd-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
index a92b1c9..2aab1e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
index 145ffd9..bff13c18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
index 4461a28..537ed0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfma-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
index 804cfa0..7710aa7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
index 7c55586..479d45e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnma-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
index ce11509..1eeb6a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wfnms-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
index 8269dfa..46e6740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
index 3675388..4f4aaa8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
index 813a9a6..73bc45b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wmul-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
index 7ce910c..7cdd2d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
index 75d49bc..d789566 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -ffast-math -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
index f49acc1..6e9456b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wred-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "wred-2.c"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
index eea9540..6d95914 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
index 1048d29..9e67ad1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
index ac4bfe2..f92ffd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
index 619c0c7..69883e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/wsub-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -mrvv-max-lmul=m8 -fdump-tree-optimized" } */
 
 #include "def.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
index 213c4d0..be1e4cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
index fd99a5d..c97bde0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model" } */
 #include <stdint-gcc.h>
 
 #define TEST_TYPE(TYPE1, TYPE2, N)                                             \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
index a2d38a8..4a34f8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
index 8b054b7..e72a5c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
index 34d34e7..0fe15ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
index 2dfcc6d..8f47df6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
index d7ee31f..a02cbd4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */
+/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fdump-tree-vect-details" } */
 
 #include "template-1.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 25b34ee..0699cb7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
    Use extern here so that we get a known alignment, lest
    DATA_ALIGNMENT force us to make the scan pattern accomodate
    code for different alignments depending on word size.
-** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m2" "-mrvv-max-lmul=m4" "-mrvv-max-lmul=m8" "-mrvv-vector-bits=zvl" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
 **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
@@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
 */
 
 /*
-** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } }
+** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "-mrvv-max-lmul=dynamic" "-mrvv-max-lmul=m8" "-mrvv-max-lmul=m4" "-mrvv-vector-bits=zvl" } } }
 **        lla\s+[ta][0-7],a_a
 **        lla\s+[ta][0-7],a_b
 **        vsetivli\s+zero,16,e32,m8,ta,ma
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 1161ccb..6a854c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16;
 */
 
 /*
-** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f1: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl1re8.v\s+v1,0\(a1\)
 **	vs1r.v\s+v1,0\(a0\)
 **	ret
@@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b)
 */
 
 /*
-** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f2: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl2re8.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
@@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b)
 */
 
 /*
-** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } }
+** f3: { target {  { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b -mrvv-max-lmul=dynamic" } } }
 **	vl2re16.v\s+v2,0\(a1\)
 **	vs2r.v\s+v2,0\(a0\)
 **	ret
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index fe404c6..8c4e916 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -47,16 +47,16 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \
 	"" "-O3 -ftree-vectorize"
 
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m8} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=dynamic} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m8} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=dynamic} ]
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m8} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=dynamic} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m8} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=dynamic} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/partial/*.\[cS\]]] \
     "" "$op"
@@ -80,12 +80,12 @@ foreach op $AUTOVEC_TEST_OPTS {
 
 # widening operation only test on LMUL < 8
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
-  {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} ]
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O3 -mrvv-max-lmul=m4} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m1} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m2} \
+  {-ftree-vectorize -O2 -mrvv-max-lmul=m4} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/widen/*.\[cS\]]] \
     "" "$op"
@@ -97,26 +97,26 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]]
 
 # gather-scatter tests
 set AUTOVEC_TEST_OPTS [list \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \
-  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ]
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -fno-vect-cost-model -ffast-math} \
+  {-ftree-vectorize -O2 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} ]
 foreach op $AUTOVEC_TEST_OPTS {
   dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \
     "" "$op"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
index 91bd4ca..4e5a4b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -mrvv-max-lmul=m2 -fno-vect-cost-model" } */
 
 #include <stdint-gcc.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
index 703e47e..96bea3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 -mrvv-max-lmul=m8 -mrvv-vector-bits=zvl -O2" } */
 
 struct a_struct
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
index 5665a23..489dae8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */
 
 int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right,
     safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2,
author	demin.han <demin.han@starfivetech.com>	2024-03-13 18:43:26 +0800
committer	demin.han <demin.han@starfivetech.com>	2024-03-20 16:38:10 +0800
commit	cd1ce3b326d49c16bade1fb76daa2ee67586efc9 (patch)
tree	4414dfaae2c2230e164b8300cfe018823125653f /gcc
parent	6a55e39bdb1fdb570730c08413ebbe744e493411 (diff)
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