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| author | Richard Henderson <rth@redhat.com> | 2005-06-28 00:46:40 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2005-06-28 00:46:40 -0700 |
| commit | cabddb237f08b09f7e25dc53bcb36de370f8e8df (patch) | |
| tree | 6089ebb6bd183e5977971851f405fbb4fe8438c9 /gcc | |
| parent | 9009820b36c750c043ddf1cd885ef5ad51304350 (diff) | |
| download | gcc-cabddb237f08b09f7e25dc53bcb36de370f8e8df.zip gcc-cabddb237f08b09f7e25dc53bcb36de370f8e8df.tar.gz gcc-cabddb237f08b09f7e25dc53bcb36de370f8e8df.tar.bz2 | |
ia64.c (ia64_expand_vcondu_v2si): Generate proper comparison operations.
* config/ia64/ia64.c (ia64_expand_vcondu_v2si): Generate proper
comparison operations.
(ia64_expand_vecint_minmax): Fix size of xops.
* config/ia64/vect.md (umax<VECINT>3): Fix fallback pattern typo.
(vec_shl_<VECINT>, vec_shr_<VECINT>): New.
From-SVN: r101375
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.c | 8 | ||||
| -rw-r--r-- | gcc/config/ia64/vect.md | 22 |
3 files changed, 34 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4a53775..9ee2541 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2005-06-27 Richard Henderson <rth@redhat.com> + * config/ia64/ia64.c (ia64_expand_vcondu_v2si): Generate proper + comparison operations. + (ia64_expand_vecint_minmax): Fix size of xops. + * config/ia64/vect.md (umax<VECINT>3): Fix fallback pattern typo. + (vec_shl_<VECINT>, vec_shr_<VECINT>): New. + +2005-06-27 Richard Henderson <rth@redhat.com> + * tree-vect-transform.c (get_initial_def_for_reduction): Use correct type for DEF and INIT_VAL. Pretend MIN/MAX need epilogue adjustment. diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 45fb73e..5109d4f 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -1533,11 +1533,13 @@ ia64_expand_vcondu_v2si (enum rtx_code code, rtx operands[]) /* With the results of the comparisons, emit conditional moves. */ dl = gen_reg_rtx (SImode); - x = gen_rtx_IF_THEN_ELSE (SImode, bl, op1l, op2l); + x = gen_rtx_NE (VOIDmode, bl, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (SImode, x, op1l, op2l); emit_insn (gen_rtx_SET (VOIDmode, dl, x)); dh = gen_reg_rtx (SImode); - x = gen_rtx_IF_THEN_ELSE (SImode, bh, op1h, op2h); + x = gen_rtx_NE (VOIDmode, bh, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (SImode, x, op1h, op2h); emit_insn (gen_rtx_SET (VOIDmode, dh, x)); /* Merge the two partial results back into a vector. */ @@ -1613,7 +1615,7 @@ bool ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode, rtx operands[]) { - rtx xops[5]; + rtx xops[6]; /* These four combinations are supported directly. */ if (mode == V8QImode && (code == UMIN || code == UMAX)) diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index c9a4c54..dc6e0f7 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -214,7 +214,7 @@ (define_expand "umax<mode>3" [(set (match_operand:VECINT 0 "gr_register_operand" "") - (smax:VECINT (match_operand:VECINT 1 "gr_register_operand" "") + (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "") (match_operand:VECINT 2 "gr_register_operand" "")))] "" { @@ -311,6 +311,26 @@ "pshr<vecsize>.u %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) +(define_expand "vec_shl_<mode>" + [(set (match_operand:VECINT 0 "gr_register_operand" "") + (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "") + (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) + +(define_expand "vec_shr_<mode>" + [(set (match_operand:VECINT 0 "gr_register_operand" "") + (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "") + (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) + (define_expand "vcond<mode>" [(set (match_operand:VECINT 0 "gr_register_operand" "") (if_then_else:VECINT |