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| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2007-10-28 11:37:50 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2007-10-28 11:37:50 +0000 |
| commit | c8d6f9e7e5f7cc755dbcaa74021002d8c593543b (patch) | |
| tree | 54a19ff7511e2d7c5dc951694e90fddf64b8d607 /gcc | |
| parent | 9a4a025a01f27acc76bb275cf5972c3f0ad493a6 (diff) | |
| download | gcc-c8d6f9e7e5f7cc755dbcaa74021002d8c593543b.zip gcc-c8d6f9e7e5f7cc755dbcaa74021002d8c593543b.tar.gz gcc-c8d6f9e7e5f7cc755dbcaa74021002d8c593543b.tar.bz2 | |
mips.md: Add combiner patterns for DImode extensions of HImode and QImode truncations.
gcc/
* config/mips/mips.md: Add combiner patterns for DImode extensions
of HImode and QImode truncations. Reformat HImode <- QImode pattern
for consistency.
From-SVN: r129695
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 69 |
2 files changed, 43 insertions, 32 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e55a92a..9e772d6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2007-10-28 Richard Sandiford <rsandifo@nildram.co.uk> + * config/mips/mips.md: Add combiner patterns for DImode extensions + of HImode and QImode truncations. Reformat HImode <- QImode pattern + for consistency. + +2007-10-28 Richard Sandiford <rsandifo@nildram.co.uk> + PR target/33895 * config/mips/mips.c (mips_output_dwarf_dtprel): Add ATTRIBUTE_UNUSED. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1f7503e..18879ec 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2366,68 +2366,73 @@ (set_attr "mode" "SI")]) -;; Combiner patterns for truncate/sign_extend combinations. They use -;; the shift/truncate patterns above. +;; Combiner patterns for truncate/sign_extend combinations. The SI versions +;; use the shift/truncate patterns above. -(define_insn_and_split "" - [(set (match_operand:SI 0 "register_operand" "=d") - (sign_extend:SI - (truncate:HI (match_operand:DI 1 "register_operand" "d"))))] +(define_insn_and_split "*extenddi_truncate<mode>" + [(set (match_operand:DI 0 "register_operand" "=d") + (sign_extend:DI + (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "#" "&& reload_completed" [(set (match_dup 2) (ashift:DI (match_dup 1) - (const_int 48))) + (match_dup 3))) (set (match_dup 0) - (truncate:SI (ashiftrt:DI (match_dup 2) - (const_int 48))))] - { operands[2] = gen_lowpart (DImode, operands[0]); }) + (ashiftrt:DI (match_dup 2) + (match_dup 3)))] +{ + operands[2] = gen_lowpart (DImode, operands[0]); + operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); +}) -(define_insn_and_split "" +(define_insn_and_split "*extendsi_truncate<mode>" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI - (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] + (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "#" "&& reload_completed" [(set (match_dup 2) (ashift:DI (match_dup 1) - (const_int 56))) + (match_dup 3))) (set (match_dup 0) (truncate:SI (ashiftrt:DI (match_dup 2) - (const_int 56))))] - { operands[2] = gen_lowpart (DImode, operands[0]); }) - + (match_dup 3))))] +{ + operands[2] = gen_lowpart (DImode, operands[0]); + operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); +}) ;; Combiner patterns to optimize truncate/zero_extend combinations. -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (truncate:HI - (match_operand:DI 1 "register_operand" "d"))))] +(define_insn "*zero_extend<mode>_trunchi" + [(set (match_operand:GPR 0 "register_operand" "=d") + (zero_extend:GPR + (truncate:HI (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "andi\t%0,%1,0xffff" - [(set_attr "type" "logical") - (set_attr "mode" "SI")]) + [(set_attr "type" "logical") + (set_attr "mode" "<MODE>")]) -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=d") - (zero_extend:SI (truncate:QI - (match_operand:DI 1 "register_operand" "d"))))] +(define_insn "*zero_extend<mode>_truncqi" + [(set (match_operand:GPR 0 "register_operand" "=d") + (zero_extend:GPR + (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "andi\t%0,%1,0xff" - [(set_attr "type" "logical") - (set_attr "mode" "SI")]) + [(set_attr "type" "logical") + (set_attr "mode" "<MODE>")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=d") - (zero_extend:HI (truncate:QI - (match_operand:DI 1 "register_operand" "d"))))] + (zero_extend:HI + (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] "TARGET_64BIT && !TARGET_MIPS16" "andi\t%0,%1,0xff" - [(set_attr "type" "logical") - (set_attr "mode" "HI")]) + [(set_attr "type" "logical") + (set_attr "mode" "HI")]) ;; ;; .................... |