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| author | Kito Cheng <kito.cheng@sifive.com> | 2023-02-20 21:47:01 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-02-20 23:26:28 +0800 |
| commit | b943d5771e1cdaba3004c4ca692ffa9e1a094f8d (patch) | |
| tree | 9056af6899ae2c588adb56ee8c0d2eb87e8fe728 /gcc | |
| parent | 02d8ab3e4e2f3d9dc12157a98c976d6698e71e29 (diff) | |
| download | gcc-b943d5771e1cdaba3004c4ca692ffa9e1a094f8d.zip gcc-b943d5771e1cdaba3004c4ca692ffa9e1a094f8d.tar.gz gcc-b943d5771e1cdaba3004c4ca692ffa9e1a094f8d.tar.bz2 | |
RISC-V: prefetch.* only take base register with zero-offset for the address
Catched by running gcc.c-torture/execute/builtin-prefetch-2.c with
-march=rv64gc_zicbop.
gcc/ChangeLog:
* config/riscv/riscv.md (prefetch): Use r instead of p for the
address operand.
(riscv_prefetchi_<mode>): Ditto.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 487059e..a5507fad 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3066,7 +3066,7 @@ ) (define_insn "prefetch" - [(prefetch (match_operand 0 "address_operand" "p") + [(prefetch (match_operand 0 "address_operand" "r") (match_operand 1 "imm5_operand" "i") (match_operand 2 "const_int_operand" "n"))] "TARGET_ZICBOP" @@ -3080,7 +3080,7 @@ }) (define_insn "riscv_prefetchi_<mode>" - [(unspec_volatile:X [(match_operand:X 0 "address_operand" "p") + [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") (match_operand:X 1 "imm5_operand" "i")] UNSPECV_PREI)] "TARGET_ZICBOP" |