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| author | Richard Sandiford <richard.sandiford@arm.com> | 2020-02-03 21:12:35 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2020-02-06 17:26:59 +0000 |
| commit | b65a1eb3fae53f2e1ea1ef8c1164f490d55855a1 (patch) | |
| tree | ae82e4a261990680af6789d0c4369270e977a0e2 /gcc | |
| parent | 88ec0e8dbe6be8ac466c15ee057a8b1d4926fa8e (diff) | |
| download | gcc-b65a1eb3fae53f2e1ea1ef8c1164f490d55855a1.zip gcc-b65a1eb3fae53f2e1ea1ef8c1164f490d55855a1.tar.gz gcc-b65a1eb3fae53f2e1ea1ef8c1164f490d55855a1.tar.bz2 | |
aarch64: Add an extra sbfiz pattern [PR87763]
This patch matches another form of sbfiz, in which the input
has DImode and the output has SImode. It fixes a regression
in gcc.target/aarch64/lsl_asr_sbfiz.c from GCC 8.
2020-02-06 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR rtl-optimization/87763
* config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 15 |
2 files changed, 20 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fe29d3..efbbbf0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-02-06 Richard Sandiford <richard.sandiford@arm.com> + + PR rtl-optimization/87763 + * config/aarch64/aarch64.md (*ashiftsi_extvdi_bfiz): New pattern. + 2020-02-06 Delia Burduv <delia.burduv@arm.com> * config/aarch64/aarch64-simd-builtins.def diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4f58981..90eebce 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5771,6 +5771,21 @@ [(set_attr "type" "bfx")] ) +(define_insn "*ashiftsi_extvdi_bfiz" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI + (match_operator:SI 4 "subreg_lowpart_operator" + [(sign_extract:DI + (match_operand:DI 1 "register_operand" "r") + (match_operand 2 "aarch64_simd_shift_imm_offset_si") + (const_int 0))]) + (match_operand 3 "aarch64_simd_shift_imm_si")))] + "IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]), + 1, GET_MODE_BITSIZE (SImode) - 1)" + "sbfiz\\t%w0, %w1, %3, %2" + [(set_attr "type" "bfx")] +) + ;; When the bit position and width of the equivalent extraction add up to 32 ;; we can use a W-reg LSL instruction taking advantage of the implicit ;; zero-extension of the X-reg. |