RISC-V: Add testcases for vector truncate after .SAT_SUB

This patch would like to add the test cases of the vector truncate after
.SAT_SUB.  Aka:

  #define DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_trunc_##OUT_T##_fmt_1 (OUT_T *out, IN_T *op_1, IN_T y, \
  				     unsigned limit)                 \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        IN_T x = op_1[i];                                              \
        out[i] = (OUT_T)(x >= y ? x - y : 0);                          \
      }                                                                \
  }

The below 3 cases are included.

DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
	test macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

8 files changed, 331 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index d5c81fb..a311603 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -310,4 +310,23 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
 #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
   vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
 
+/******************************************************************************/
+/* Saturation Sub Truncated (Unsigned and Signed)                             */
+/******************************************************************************/
+#define DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)                   \
+void __attribute__((noinline))                                       \
+vec_sat_u_sub_trunc_##OUT_T##_fmt_1 (OUT_T *out, IN_T *op_1, IN_T y, \
+				     unsigned limit)                 \
+{                                                                    \
+  unsigned i;                                                        \
+  for (i = 0; i < limit; i++)                                        \
+    {                                                                \
+      IN_T x = op_1[i];                                              \
+      out[i] = (OUT_T)(x >= y ? x - y : 0);                          \
+    }                                                                \
+}
+
+#define RUN_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T, out, op_1, y, N) \
+  vec_sat_u_sub_trunc_##OUT_T##_fmt_1(out, op_1, y, N)
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h
new file mode 100644
index 0000000..c79b180
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_scalar.h
@@ -0,0 +1,27 @@
+#ifndef HAVE_DEFINED_VEC_SAT_BINARY_SCALAR
+#define HAVE_DEFINED_VEC_SAT_BINARY_SCALAR
+
+int
+main ()
+{
+  unsigned i, k;
+  OUT_T out[N];
+
+  for (i = 0; i < sizeof (expect_data) / sizeof (expect_data[0]); i++)
+    {
+      IN_T *op_1 = op_1_data[i];
+      IN_T op_2 = op_2_data[i];
+      OUT_T *expect = expect_data[i];
+
+      RUN_VEC_SAT_BINARY (OUT_T, IN_T, out, op_1, op_2, N);
+
+      for (k = 0; k < N; k++)
+	if (out[k] != expect[k])
+	  __builtin_abort ();
+    }
+
+  return 0;
+}
+
+#endif
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
new file mode 100644
index 0000000..dd9e399
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_trunc_uint8_t_fmt_1:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** ...
+** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
new file mode 100644
index 0000000..738d146
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_trunc_uint16_t_fmt_1:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** ...
+** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
new file mode 100644
index 0000000..b008b21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_sub_trunc_uint32_t_fmt_1:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** ...
+** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c
new file mode 100644
index 0000000..324648e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-1.c
@@ -0,0 +1,74 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define OUT_T              uint8_t
+#define IN_T               uint16_t
+#define N                  16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 
+
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)
+
+OUT_T expect_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    254, 255, 4, 0,
+    254, 255, 4, 0,
+    254, 255, 4, 0,
+    254, 255, 4, 0,
+  },
+  {
+    23, 0, 0, 2,
+    23, 0, 0, 2,
+    23, 0, 0, 2,
+    23, 0, 0, 2,
+  },
+  {
+    254, 43, 0, 255,
+    254, 43, 0, 255,
+    254, 43, 0, 255,
+    254, 43, 0, 255,
+  },
+};
+
+IN_T op_1_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    65535, 256, 5, 0,
+    65535, 256, 5, 0,
+    65535, 256, 5, 0,
+    65535, 256, 5, 0,
+  },
+  {
+    65535, 1024, 5, 65002,
+    65535, 1024, 5, 65002,
+    65535, 1024, 5, 65002,
+    65535, 1024, 5, 65002,
+  },
+  {
+    65535, 300, 256, 512,
+    65535, 300, 256, 512,
+    65535, 300, 256, 512,
+    65535, 300, 256, 512,
+  },
+};
+
+IN_T op_2_data[] = {
+  0,
+  1,
+  65000,
+  257,
+};
+
+#include "vec_sat_binary_scalar.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c
new file mode 100644
index 0000000..a9bf1dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-2.c
@@ -0,0 +1,74 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define OUT_T              uint16_t
+#define IN_T               uint32_t
+#define N                  16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 
+
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)
+
+OUT_T expect_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    65534, 65535, 4, 0,
+    65534, 65535, 4, 0,
+    65534, 65535, 4, 0,
+    65534, 65535, 4, 0,
+  },
+  {
+    43, 0, 0, 2,
+    43, 0, 0, 2,
+    43, 0, 0, 2,
+    43, 0, 0, 2,
+  },
+  {
+    65532, 34484, 0, 65535,
+    65532, 34484, 0, 65535,
+    65532, 34484, 0, 65535,
+    65532, 34484, 0, 65535,
+  },
+};
+
+IN_T op_1_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    4294967295, 65536, 5, 0,
+    4294967295, 65536, 5, 0,
+    4294967295, 65536, 5, 0,
+    4294967295, 65536, 5, 0,
+  },
+  {
+    4294967295, 1024, 5, 4294967254,
+    4294967295, 1024, 5, 4294967254,
+    4294967295, 1024, 5, 4294967254,
+    4294967295, 1024, 5, 4294967254,
+  },
+  {
+    4294967295, 100023, 65536, 131074,
+    4294967295, 100023, 65536, 131074,
+    4294967295, 100023, 65536, 131074,
+    4294967295, 100023, 65536, 131074,
+  },
+};
+
+IN_T op_2_data[] = {
+  0,
+  1,
+  4294967252,
+  65539,
+};
+
+#include "vec_sat_binary_scalar.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c
new file mode 100644
index 0000000..1ea7467
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-run-3.c
@@ -0,0 +1,74 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+
+#define OUT_T              uint32_t
+#define IN_T               uint64_t
+#define N                  16
+#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_TRUNC_FMT_1 
+
+DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(OUT_T, IN_T)
+
+OUT_T expect_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    4294967294, 4294967295, 4, 0,
+    4294967294, 4294967295, 4, 0,
+    4294967294, 4294967295, 4, 0,
+    4294967294, 4294967295, 4, 0,
+  },
+  {
+    10, 0, 0, 2,
+    10, 0, 0, 2,
+    10, 0, 0, 2,
+    10, 0, 0, 2,
+  },
+  {
+    4294967288, 99995992, 0, 1,
+    4294967288, 99995992, 0, 1,
+    4294967288, 99995992, 0, 1,
+    4294967288, 99995992, 0, 1,
+  },
+};
+
+IN_T op_1_data[][N] = {
+  {
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+    0, 0, 0, 0,
+  },
+  {
+    18446744073709551615u, 4294967296, 5, 0,
+    18446744073709551615u, 4294967296, 5, 0,
+    18446744073709551615u, 4294967296, 5, 0,
+    18446744073709551615u, 4294967296, 5, 0,
+  },
+  {
+    18446744073709551615u, 1024, 5, 18446744073709551607u,
+    18446744073709551615u, 1024, 5, 18446744073709551607u,
+    18446744073709551615u, 1024, 5, 18446744073709551607u,
+    18446744073709551615u, 1024, 5, 18446744073709551607u,
+  },
+  {
+    18446744073709551615u, 4394963295, 65536, 4294967304,
+    18446744073709551615u, 4394963295, 65536, 4294967304,
+    18446744073709551615u, 4394963295, 65536, 4294967304,
+    18446744073709551615u, 4394963295, 65536, 4294967304,
+  },
+};
+
+IN_T op_2_data[] = {
+  0,
+  1,
+  18446744073709551605u,
+  4294967303,
+};
+
+#include "vec_sat_binary_scalar.h"