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| author | Richard Earnshaw <rearnsha@arm.com> | 2002-07-22 17:41:27 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2002-07-22 17:41:27 +0000 |
| commit | b41caf7c04d68a4c063607b40b0fafce9e06f009 (patch) | |
| tree | 2aefa72d7cbbdc535bac1b7a509056a082f6e665 /gcc | |
| parent | 492e99345fa6d4649d6f583243ed02e972f66c61 (diff) | |
| download | gcc-b41caf7c04d68a4c063607b40b0fafce9e06f009.zip gcc-b41caf7c04d68a4c063607b40b0fafce9e06f009.tar.gz gcc-b41caf7c04d68a4c063607b40b0fafce9e06f009.tar.bz2 | |
arm.md (movqi): If optimizing and we can create pseudos...
* arm.md (movqi): If optimizing and we can create pseudos, use
a ZERO_EXTEND to load from memory, then copy the result into the
target.
(movhi): Likewise, but only for ARMv4.
From-SVN: r55655
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 21 |
2 files changed, 25 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 81e9c22..5dc4407 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2002-07-22 Richard Earnshaw <rearnsha@arm.com> + + * arm.md (movqi): If optimizing and we can create pseudos, use + a ZERO_EXTEND to load from memory, then copy the result into the + target. + (movhi): Likewise, but only for ARMv4. + 2002-07-22 Neil Booth <neil@daikokuya.co.uk> * ssa-ccp.c (PHI_PARMS): Remove. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8e4b9c0..8bd129c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4417,6 +4417,14 @@ emit_insn (gen_movsi (reg, GEN_INT (val))); operands[1] = gen_lowpart (HImode, reg); } + else if (arm_arch4 && !no_new_pseudos && optimize > 0 + && GET_CODE (operands[1]) == MEM) + { + rtx reg = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extendhisi2 (reg, operands[1])); + operands[1] = gen_lowpart (HImode, reg); + } else if (!arm_arch4) { /* Note: We do not have to worry about TARGET_MMU_TRAPS @@ -4814,9 +4822,16 @@ emit_insn (gen_movsi (reg, operands[1])); operands[1] = gen_lowpart (QImode, reg); } - if (GET_CODE (operands[0]) == MEM) - operands[1] = force_reg (QImode, operands[1]); - } + if (GET_CODE (operands[1]) == MEM && optimize > 0) + { + rtx reg = gen_reg_rtx (SImode); + + emit_insn (gen_zero_extendqisi2 (reg, operands[1])); + operands[1] = gen_lowpart (QImode, reg); + } + if (GET_CODE (operands[0]) == MEM) + operands[1] = force_reg (QImode, operands[1]); + } } else /* TARGET_THUMB */ { |