nvptx: Add (experimental) support for HFmode with -misa=sm_53

The recent flurry of activity around HFmode on gcc-patches intrigued me
to investigate adding HFmode support to the nvptx backend.  NVidia GPUs
with an SM ISA above 5.3 support IEEE 16-bit floating point instructions.
Hence, this patch adds support for -misa=sm_53, and implements some
backend patterns/insns sufficient for a proof-of-concept prototype.

The following has been tested on nvptx-none, hosted on x86_64-pc-linux-gnu
with a "make" and "make -k check" with no new failures.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (ptx_isa): Add PTX_ISA_SM53 ISA level
	to enumeration.
	* config/nvptx/nvptx.opt: Add sm_53 to -misa.
	* config/nvptx/nvptx-modes.def: Add support for HFmode.
	* config/nvptx/nvptx.h (TARGET_SM53):
	New helper macro to conditionalize functionality on target ISA.
	* config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
	support for the new ISA levels.
	* config/nvptx/nvptx.c (nvtx_ptx_type_from_mode): Support new HFmode
	with the ".f16" suffix/qualifier.
	(nvptx_file_start): Add support for TARGET_SM53.
	(nvptx_omp_device_kind_arch_isa): Add support for TARGET_SM53
	and tweak TARGET_SM35.
	(nvptx_scalar_mode_supported_p): Target hook with conditional
	HFmode support on TARGET_SM53 and higher.
	(nvptx_libgcc_floating_mode_supported_p): Likewise.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Use nvptx_scalar_mode_supported_p.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Likewise, use new hook.
	* config/nvptx/nvptx.md (*movhf_insn): New define_insn.
	(movhf): New define_expand for HFmode moves.
	(addhf3, subhf3, mulhf, extendhf<mode>2, trunc<mode>hf2): New
	instructions conditional on TARGET_SM53 (i.e. -misa=sm_53).

gcc/testsuite/ChangeLog:

	* gcc.target/nvptx/float16-1.c: New test case.

8 files changed, 174 insertions, 4 deletions

diff --git a/gcc/config/nvptx/nvptx-c.c b/gcc/config/nvptx/nvptx-c.c
index 72594a82e..7efdf70 100644
--- a/gcc/config/nvptx/nvptx-c.c
+++ b/gcc/config/nvptx/nvptx-c.c
@@ -39,7 +39,9 @@ nvptx_cpu_cpp_builtins (void)
     cpp_define (parse_in, "__nvptx_softstack__");
   if (TARGET_UNIFORM_SIMT)
     cpp_define (parse_in,"__nvptx_unisimt__");
-  if (TARGET_SM35)
+  if (TARGET_SM53)
+    cpp_define (parse_in, "__PTX_SM__=530");
+  else if (TARGET_SM35)
     cpp_define (parse_in, "__PTX_SM__=350");
   else
     cpp_define (parse_in,"__PTX_SM__=300");
diff --git a/gcc/config/nvptx/nvptx-modes.def b/gcc/config/nvptx/nvptx-modes.def
index ff61b36..cc19a26 100644
--- a/gcc/config/nvptx/nvptx-modes.def
+++ b/gcc/config/nvptx/nvptx-modes.def
@@ -1,3 +1,5 @@
+FLOAT_MODE (HF, 2, ieee_half_format);  /* HFmode */
+
 VECTOR_MODE (INT, SI, 2);  /* V2SI */
 
 VECTOR_MODE (INT, DI, 2);  /* V2DI */
diff --git a/gcc/config/nvptx/nvptx-opts.h b/gcc/config/nvptx/nvptx-opts.h
index bfa926e..f7371dc 100644
--- a/gcc/config/nvptx/nvptx-opts.h
+++ b/gcc/config/nvptx/nvptx-opts.h
@@ -23,7 +23,8 @@
 enum ptx_isa
 {
   PTX_ISA_SM30,
-  PTX_ISA_SM35
+  PTX_ISA_SM35,
+  PTX_ISA_SM53
 };
 
 enum ptx_version
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 951252e..445d7ce 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -294,6 +294,8 @@ nvptx_ptx_type_from_mode (machine_mode mode, bool promote)
     case E_DImode:
       return ".u64";
 
+    case E_HFmode:
+      return ".f16";
     case E_SFmode:
       return ".f32";
     case E_DFmode:
@@ -5406,7 +5408,9 @@ nvptx_file_start (void)
     fputs ("\t.version\t6.3\n", asm_out_file);
   else
     fputs ("\t.version\t3.1\n", asm_out_file);
-  if (TARGET_SM35)
+  if (TARGET_SM53)
+    fputs ("\t.target\tsm_53\n", asm_out_file);
+  else if (TARGET_SM35)
     fputs ("\t.target\tsm_35\n", asm_out_file);
   else
     fputs ("\t.target\tsm_30\n", asm_out_file);
@@ -5717,7 +5721,9 @@ nvptx_omp_device_kind_arch_isa (enum omp_device_kind_arch_isa trait,
       if (strcmp (name, "sm_30") == 0)
 	return !TARGET_SM35;
       if (strcmp (name, "sm_35") == 0)
-	return TARGET_SM35;
+	return TARGET_SM35 && !TARGET_SM53;
+      if (strcmp (name, "sm_53") == 0)
+	return TARGET_SM53;
       return 0;
     default:
       gcc_unreachable ();
@@ -6614,6 +6620,24 @@ nvptx_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED,
 }
 
 static bool
+nvptx_scalar_mode_supported_p (scalar_mode mode)
+{
+  if (mode == HFmode && TARGET_SM53)
+    return true;
+
+  return default_scalar_mode_supported_p (mode);
+}
+
+static bool
+nvptx_libgcc_floating_mode_supported_p (scalar_float_mode mode)
+{
+  if (mode == HFmode && TARGET_SM53)
+    return true;
+
+  return default_libgcc_floating_mode_supported_p (mode);
+}
+
+static bool
 nvptx_vector_mode_supported (machine_mode mode)
 {
   return (mode == V2SImode
@@ -6935,6 +6959,13 @@ nvptx_libc_has_function (enum function_class fn_class, tree type)
 #undef TARGET_CANNOT_FORCE_CONST_MEM
 #define TARGET_CANNOT_FORCE_CONST_MEM nvptx_cannot_force_const_mem
 
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P nvptx_scalar_mode_supported_p
+
+#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
+#define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
+  nvptx_libgcc_floating_mode_supported_p
+
 #undef TARGET_VECTOR_MODE_SUPPORTED_P
 #define TARGET_VECTOR_MODE_SUPPORTED_P nvptx_vector_mode_supported
 
diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h
index d367174..c3480cc 100644
--- a/gcc/config/nvptx/nvptx.h
+++ b/gcc/config/nvptx/nvptx.h
@@ -87,6 +87,7 @@
 #define STACK_SIZE_MODE Pmode
 
 #define TARGET_SM35 (ptx_isa_option >= PTX_ISA_SM35)
+#define TARGET_SM53 (ptx_isa_option >= PTX_ISA_SM53)
 
 #define TARGET_PTX_6_3 (ptx_version_option >= PTX_VERSION_6_3)
 
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index b7a0393..da4ac8f 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -273,6 +273,48 @@
 }
   [(set_attr "subregs_ok" "true")])
 
+(define_insn "*movhf_insn"
+  [(set (match_operand:HF 0 "nonimmediate_operand" "=R,R,m")
+	(match_operand:HF 1 "nonimmediate_operand" "R,m,R"))]
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
+  "@
+   %.\\tmov.b16\\t%0, %1;
+   %.\\tld.b16\\t%0, %1;
+   %.\\tst.b16\\t%0, %1;")
+
+(define_expand "movhf"
+  [(set (match_operand:HF 0 "nonimmediate_operand" "")
+	(match_operand:HF 1 "nonimmediate_operand" ""))]
+  ""
+{
+  /* Load HFmode constants as SFmode with an explicit FLOAT_TRUNCATE.  */
+  if (CONST_DOUBLE_P (operands[1]))
+    {
+      rtx tmp1 = gen_reg_rtx (SFmode);
+      REAL_VALUE_TYPE d = *CONST_DOUBLE_REAL_VALUE (operands[1]);
+      real_convert (&d, SFmode, &d);
+      emit_move_insn (tmp1, const_double_from_real_value (d, SFmode));
+
+      if (!REG_P (operands[0]))
+	{
+	  rtx tmp2 = gen_reg_rtx (HFmode);
+	  emit_insn (gen_truncsfhf2 (tmp2, tmp1));
+	  emit_move_insn (operands[0], tmp2);
+	}
+      else
+        emit_insn (gen_truncsfhf2 (operands[0], tmp1));
+      DONE;
+    }
+
+  if (MEM_P (operands[0]) && !REG_P (operands[1]))
+    {
+      rtx tmp = gen_reg_rtx (HFmode);
+      emit_move_insn (tmp, operands[1]);
+      emit_move_insn (operands[0], tmp);
+      DONE;
+    }
+})
+
 (define_insn "load_arg_reg<mode>"
   [(set (match_operand:QHIM 0 "nvptx_register_operand" "=R")
 	(unspec:QHIM [(match_operand 1 "const_int_operand" "n")]
@@ -1078,6 +1120,29 @@
   "flag_unsafe_math_optimizations"
   "%.\\tex2.approx%t0\\t%0, %1;")
 
+;; HFmode floating point arithmetic.
+
+(define_insn "addhf3"
+  [(set (match_operand:HF 0 "nvptx_register_operand" "=R")
+	(plus:HF (match_operand:HF 1 "nvptx_register_operand" "R")
+		 (match_operand:HF 2 "nvptx_register_operand" "R")))]
+  "TARGET_SM53"
+  "%.\\tadd.f16\\t%0, %1, %2;")
+
+(define_insn "subhf3"
+  [(set (match_operand:HF 0 "nvptx_register_operand" "=R")
+	(minus:HF (match_operand:HF 1 "nvptx_register_operand" "R")
+		  (match_operand:HF 2 "nvptx_register_operand" "R")))]
+  "TARGET_SM53"
+  "%.\\tsub.f16\\t%0, %1, %2;")
+
+(define_insn "mulhf3"
+  [(set (match_operand:HF 0 "nvptx_register_operand" "=R")
+	(mult:HF (match_operand:HF 1 "nvptx_register_operand" "R")
+		 (match_operand:HF 2 "nvptx_register_operand" "R")))]
+  "TARGET_SM53"
+  "%.\\tmul.f16\\t%0, %1, %2;")
+
 ;; Conversions involving floating point
 
 (define_insn "extendsfdf2"
@@ -1171,6 +1236,18 @@
   ""
   "%.\\tcvt<FPINT2:fpint2_roundingmode>.s%T0%t1\\t%0, %1;")
 
+(define_insn "extendhf<mode>2"
+  [(set (match_operand:SDFM 0 "nvptx_register_operand" "=R")
+	(float_extend:SDFM (match_operand:HF 1 "nvptx_register_operand" "R")))]
+  "TARGET_SM53"
+  "%.\\tcvt%t0%t1\\t%0, %1;")
+
+(define_insn "trunc<mode>hf2"
+  [(set (match_operand:HF 0 "nvptx_register_operand" "=R")
+	(float_truncate:HF (match_operand:SDFM 1 "nvptx_register_operand" "R")))]
+  "TARGET_SM53"
+  "%.\\tcvt%#%t0%t1\\t%0, %1;")
+
 ;; Vector operations
 
 (define_insn "*vec_set<mode>_0"
diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt
index 468c6ca..514f19d 100644
--- a/gcc/config/nvptx/nvptx.opt
+++ b/gcc/config/nvptx/nvptx.opt
@@ -61,6 +61,9 @@ Enum(ptx_isa) String(sm_30) Value(PTX_ISA_SM30)
 EnumValue
 Enum(ptx_isa) String(sm_35) Value(PTX_ISA_SM35)
 
+EnumValue
+Enum(ptx_isa) String(sm_53) Value(PTX_ISA_SM53)
+
 ; Default needs to be in sync with default in ASM_SPEC in nvptx.h.
 misa=
 Target RejectNegative ToLower Joined Enum(ptx_isa) Var(ptx_isa_option) Init(PTX_ISA_SM35)
diff --git a/gcc/testsuite/gcc.target/nvptx/float16-1.c b/gcc/testsuite/gcc.target/nvptx/float16-1.c
new file mode 100644
index 0000000..3a0324d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/nvptx/float16-1.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -misa=sm_53 -mptx=6.3 -ffast-math" } */
+
+_Float16 var;
+
+float load()
+{
+  return var;
+}
+
+void store(float x)
+{
+  var = x;
+}
+
+void move(_Float16 *dst, _Float16 *src)
+{
+  *dst = *src;
+}
+
+double plus(double x, double y)
+{
+  _Float16 hx = x;
+  _Float16 hy = y;
+  _Float16 hz = hx + hy;
+  return hz;
+}
+
+double minus(double x, double y)
+{
+  _Float16 hx = x;
+  _Float16 hy = y;
+  _Float16 hz = hx - hy;
+  return hz;
+}
+
+double mult(double x, double y)
+{
+  _Float16 hx = x;
+  _Float16 hy = y;
+  _Float16 hz = hx * hy;
+  return hz;
+}
+
+/* { dg-final { scan-assembler-times "ld.b16" 2 } } */
+/* { dg-final { scan-assembler-times "cvt.f32.f16" 1 } } */
+/* { dg-final { scan-assembler-times "cvt.rn.f16.f32" 1 } } */
+/* { dg-final { scan-assembler-times "st.b16" 2 } } */
+/* { dg-final { scan-assembler-times "add.f16" 1 } } */
+/* { dg-final { scan-assembler-times "sub.f16" 1 } } */
+/* { dg-final { scan-assembler-times "mul.f16" 1 } } */
+/* { dg-final { scan-assembler-times "cvt.rn.f16.f64" 6 } } */
+/* { dg-final { scan-assembler-times "cvt.f64.f16" 3 } } */