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| author | Michael Collison <michael.collison@arm.com> | 2017-06-27 17:29:06 +0000 |
|---|---|---|
| committer | Michael Collison <collison@gcc.gnu.org> | 2017-06-27 17:29:06 +0000 |
| commit | a977dc0c5e069bf198f78ed4767deac369904301 (patch) | |
| tree | d2c67ece96c2f1b064a22e78535d657cf2fde21e /gcc | |
| parent | b2cf76f3a58d065122d2ae94bf55510551ff27f4 (diff) | |
| download | gcc-a977dc0c5e069bf198f78ed4767deac369904301.zip gcc-a977dc0c5e069bf198f78ed4767deac369904301.tar.gz gcc-a977dc0c5e069bf198f78ed4767deac369904301.tar.bz2 | |
aarch64-simd.md (aarch64_combine<mode>): Directly call aarch64_split_simd_combine.
2017-06-19 Michael Collison <michael.collison@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly
call aarch64_split_simd_combine.
* (aarch64_combine_internal<mode>): Delete pattern.
* config/aarch64/aarch64.c (aarch64_split_simd_combine):
Allow register and subreg operands.
From-SVN: r249702
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 30 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 64 |
3 files changed, 41 insertions, 61 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4f0e8b85..9f7e593 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-27 Michael Collison <michael.collison@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Directly + call aarch64_split_simd_combine. + * (aarch64_combine_internal<mode>): Delete pattern. + * config/aarch64/aarch64.c (aarch64_split_simd_combine): + Allow register and subreg operands. + 2017-06-27 Jerome Lambourg <lambourg@adacore.com> * config/i386/vxworks.h (ASM_SPEC): Remove definition. No target diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 264a9c0..1cb6eeb 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2809,38 +2809,10 @@ (match_operand:VDC 2 "register_operand")] "TARGET_SIMD" { - rtx op1, op2; - if (BYTES_BIG_ENDIAN) - { - op1 = operands[2]; - op2 = operands[1]; - } - else - { - op1 = operands[1]; - op2 = operands[2]; - } - emit_insn (gen_aarch64_combine_internal<mode> (operands[0], op1, op2)); - DONE; -} -) + aarch64_split_simd_combine (operands[0], operands[1], operands[2]); -(define_insn_and_split "aarch64_combine_internal<mode>" - [(set (match_operand:<VDBL> 0 "register_operand" "=&w") - (vec_concat:<VDBL> (match_operand:VDC 1 "register_operand" "w") - (match_operand:VDC 2 "register_operand" "w")))] - "TARGET_SIMD" - "#" - "&& reload_completed" - [(const_int 0)] -{ - if (BYTES_BIG_ENDIAN) - aarch64_split_simd_combine (operands[0], operands[2], operands[1]); - else - aarch64_split_simd_combine (operands[0], operands[1], operands[2]); DONE; } -[(set_attr "type" "multiple")] ) (define_expand "aarch64_simd_combine<mode>" diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 95592f9..6bff74c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1732,41 +1732,41 @@ aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2) machine_mode dst_mode = GET_MODE (dst); gcc_assert (VECTOR_MODE_P (dst_mode)); + gcc_assert (register_operand (dst, dst_mode) + && register_operand (src1, src_mode) + && register_operand (src2, src_mode)); - if (REG_P (dst) && REG_P (src1) && REG_P (src2)) - { - rtx (*gen) (rtx, rtx, rtx); - - switch (src_mode) - { - case V8QImode: - gen = gen_aarch64_simd_combinev8qi; - break; - case V4HImode: - gen = gen_aarch64_simd_combinev4hi; - break; - case V2SImode: - gen = gen_aarch64_simd_combinev2si; - break; - case V4HFmode: - gen = gen_aarch64_simd_combinev4hf; - break; - case V2SFmode: - gen = gen_aarch64_simd_combinev2sf; - break; - case DImode: - gen = gen_aarch64_simd_combinedi; - break; - case DFmode: - gen = gen_aarch64_simd_combinedf; - break; - default: - gcc_unreachable (); - } + rtx (*gen) (rtx, rtx, rtx); - emit_insn (gen (dst, src1, src2)); - return; + switch (src_mode) + { + case V8QImode: + gen = gen_aarch64_simd_combinev8qi; + break; + case V4HImode: + gen = gen_aarch64_simd_combinev4hi; + break; + case V2SImode: + gen = gen_aarch64_simd_combinev2si; + break; + case V4HFmode: + gen = gen_aarch64_simd_combinev4hf; + break; + case V2SFmode: + gen = gen_aarch64_simd_combinev2sf; + break; + case DImode: + gen = gen_aarch64_simd_combinedi; + break; + case DFmode: + gen = gen_aarch64_simd_combinedf; + break; + default: + gcc_unreachable (); } + + emit_insn (gen (dst, src1, src2)); + return; } /* Split a complex SIMD move. */ |