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authorH.J. Lu <hjl.tools@gmail.com>2020-05-21 07:19:27 -0700
committerH.J. Lu <hjl.tools@gmail.com>2020-05-21 07:19:27 -0700
commita74630f3207d0bec63710c8c803685a0a4956986 (patch)
tree16c62153ea906d8fdb24779c3bbc46e44bfb04fa /gcc
parentbc7a4f2f9e91b3a08eff2eba759f071127f714cd (diff)
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config/i386/cpuid.h: Use hexadecimal in comments
Since Intel SDM uses hexadecimal, use hexadecimal in comments. PR target/95260 * config/i386/cpuid.h: Use hexadecimal in comments.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/i386/cpuid.h6
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 89b908f..977e766 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2020-05-21 H.J. Lu <hongjiu.lu@intel.com>
+ PR target/95260
+ * config/i386/cpuid.h: Use hexadecimal in comments.
+
+2020-05-21 H.J. Lu <hongjiu.lu@intel.com>
+
PR target/95212
* config/i386/i386-builtins.c (processor_features): Move
F_AVX512VP2INTERSECT after F_AVX512BF16.
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 9fee32a..94af491 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -125,16 +125,16 @@
#define bit_SERIALIZE (1 << 14)
#define bit_TSXLDTRK (1 << 16)
-/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
+/* XFEATURE_ENABLED_MASK register bits (%eax == 0xd, %ecx == 0) */
#define bit_BNDREGS (1 << 3)
#define bit_BNDCSR (1 << 4)
-/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
+/* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
#define bit_XSAVEOPT (1 << 0)
#define bit_XSAVEC (1 << 1)
#define bit_XSAVES (1 << 3)
-/* PT sub leaf (%eax == 14, %ecx == 0) */
+/* PT sub leaf (%eax == 0x14, %ecx == 0) */
/* %ebx */
#define bit_PTWRITE (1 << 4)