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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-08 15:00:04 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-08 15:00:04 +0100 |
| commit | a45fe62102c952072e977db6d42a8524c4dd36c1 (patch) | |
| tree | f8e00665e5a0b1711195e2bb6ffc332e0da8d749 /gcc | |
| parent | d3f78917e1310d7d00e4f955c8e5d30a777f7d35 (diff) | |
| download | gcc-a45fe62102c952072e977db6d42a8524c4dd36c1.zip gcc-a45fe62102c952072e977db6d42a8524c4dd36c1.tar.gz gcc-a45fe62102c952072e977db6d42a8524c4dd36c1.tar.bz2 | |
testsuite: Fix Advanced SIMD failures for SVE
This patch just adds some missing +nosve directives to Advanced
SIMD vectorisation tests.
gcc/testsuite/
* gcc.target/aarch64/asimd-mull-elem.c: Add +nosve.
* gcc.target/aarch64/pr98772.c: Likewise.
* gcc.target/aarch64/simd/vect_su_add_sub.c: Likewise.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr98772.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c | 2 |
3 files changed, 7 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c index 513721c..8ee7d11 100644 --- a/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c +++ b/gcc/testsuite/gcc.target/aarch64/asimd-mull-elem.c @@ -3,6 +3,8 @@ /* { dg-require-effective-target vect_float } */ /* { dg-options "-Ofast" } */ +#pragma GCC target "+nosve" + #include <arm_neon.h> void s_mult_i (int32_t* restrict res, int32_t* restrict a, int32_t b) diff --git a/gcc/testsuite/gcc.target/aarch64/pr98772.c b/gcc/testsuite/gcc.target/aarch64/pr98772.c index 6632215..8259251 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr98772.c +++ b/gcc/testsuite/gcc.target/aarch64/pr98772.c @@ -1,5 +1,8 @@ /* { dg-do run } */ /* { dg-options "-O3 -save-temps" } */ + +#pragma GCC target "+nosve" + #include <stdint.h> #include <string.h> diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c index 921c5f1..4abb8e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vect_su_add_sub.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O3" } */ +#pragma GCC target "+nosve" + typedef int __attribute__ ((mode (SI))) int32_t; typedef int __attribute__ ((mode (DI))) int64_t; typedef unsigned __attribute__ ((mode (SI))) size_t; |