RISC-V: Enable pressure-aware scheduling by default.

this patch enables pressure-aware scheduling for riscv.  There have been
various requests for it so I figured I'd just go ahead and send
the patch.

There is some slight regression in code quality for a number of
vector tests where we spill more due to different instructions order.
The ones I looked at were a mix of bad luck and/or brittle tests.
Comparing the size of the generated assembly or the number of vsetvls
for SPECint also didn't show any immediate benefit but that's obviously
not a very fine-grained analysis.

As cost and scheduling models mature I expect the situation to improve
and for now I think it's generally favorable to enable pressure-aware
scheduling so we can work with it rather than trying to find every
possible problem in advance.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add -fsched-pressure.
	* config/riscv/riscv.cc (riscv_option_override): Set sched
	pressure algorithm.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/narrow_constraint-1.c: Add
	-fno-sched-pressure.
	* gcc.target/riscv/rvv/base/narrow_constraint-17.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-18.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-19.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-20.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-21.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-22.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-23.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-24.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-25.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-26.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-27.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-28.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-29.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-30.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-31.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-4.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-5.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/narrow_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto.

27 files changed, 32 insertions, 25 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4737dcd..8233011 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -2016,6 +2016,8 @@ riscv_get_valid_option_values (int option_code,
 static const struct default_options riscv_option_optimization_table[] =
   {
     { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+    /* Enable -fsched-pressure starting at -O1.  */
+    { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
     { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
 #if TARGET_DEFAULT_ASYNC_UNWIND_TABLES == 1
     { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0f60ffe..480f312 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -65,6 +65,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "cfgloop.h"
 #include "cfgrtl.h"
 #include "sel-sched.h"
+#include "sched-int.h"
 #include "fold-const.h"
 #include "gimple-iterator.h"
 #include "gimple-expr.h"
@@ -7096,6 +7097,10 @@ riscv_option_override (void)
     sorry (
       "Current RISC-V GCC cannot support VLEN greater than 4096bit for 'V' Extension");
 
+  SET_OPTION_IF_UNSET (&global_options, &global_options_set,
+		       param_sched_pressure_algorithm,
+		       SCHED_PRESSURE_MODEL);
+
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits ();
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
index 0cdf60c..02d155d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
index 97df21d..35ef188 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-17.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
index 56c95d9..1c17b76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-18.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
index d50e497..923bc27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-19.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
index 4e77c51..6dd1b84 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-20.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
index 4f7efd5..ecf6d26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
index 92084be..2018607 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
index f9817ca..847d27c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-23.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
index 62d1f6d..603bfa2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
index 250c3fd..4f295ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-25.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
index 72e2d21..1a65239 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
index 0842700..4d70a4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-27.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
index 9c1eddf..c625d96 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-28.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
index 6988c24..109ebc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-29.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
index fe181de..b993e48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-30.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
index ae5b4ed..d0bf4a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-31.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
index 28971a0..273f15a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
index 26675bc..d75dc77 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
index 0dac85a..c96ab59 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-8.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
index 448ca85..53130d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-sched-pressure" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
index cf6470ce..fba44d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
index 4e2a717..5aabdef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
index 026b409..6db0f0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
index ca57eca..5e5e07b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
index a01b391..119e41e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-sched-pressure -fno-tree-vectorize" } */
 
 #include "riscv_vector.h"