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| author | Yufeng Zhang <yufeng.zhang@arm.com> | 2013-11-26 16:36:14 +0000 |
|---|---|---|
| committer | Yufeng Zhang <yufeng@gcc.gnu.org> | 2013-11-26 16:36:14 +0000 |
| commit | 97c34bdbe2aa20ef2e74326e0799466176af8c5f (patch) | |
| tree | d8984967b38da86b473cf3d7e3a220add54238c5 /gcc | |
| parent | 635bfae029c7f2849680a7fdecb7ab07e798564b (diff) | |
| download | gcc-97c34bdbe2aa20ef2e74326e0799466176af8c5f.zip gcc-97c34bdbe2aa20ef2e74326e0799466176af8c5f.tar.gz gcc-97c34bdbe2aa20ef2e74326e0799466176af8c5f.tar.bz2 | |
arm.c (arm_legitimize_address): Check xop1 is not a constant immediate before force_reg.
gcc/
* config/arm/arm.c (arm_legitimize_address): Check xop1 is not
a constant immediate before force_reg.
gcc/testsuite/
* gcc.target/arm/20131120.c: New test.
From-SVN: r205397
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/20131120.c | 14 |
4 files changed, 25 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 75ad19c..62dc6e0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-11-26 Yufeng Zhang <yufeng.zhang@arm.com> + + * config/arm/arm.c (arm_legitimize_address): Check xop1 is not + a constant immediate before force_reg. + 2013-11-26 Richard Biener <rguenther@suse.de> PR tree-optimization/59245 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index f88ebbc..129e428 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7118,7 +7118,8 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) xop0 = force_reg (SImode, xop0); - if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) + if (CONSTANT_P (xop1) && !CONST_INT_P (xop1) + && !symbol_mentioned_p (xop1)) xop1 = force_reg (SImode, xop1); if (ARM_BASE_REGISTER_RTX_P (xop0) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 23113f3..9cbfd41 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-11-26 Yufeng Zhang <yufeng.zhang@arm.com> + + * gcc.target/arm/20131120.c: New test. + 2013-11-26 Richard Biener <rguenther@suse.de> PR tree-optimization/59245 diff --git a/gcc/testsuite/gcc.target/arm/20131120.c b/gcc/testsuite/gcc.target/arm/20131120.c new file mode 100644 index 0000000..c370ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/20131120.c @@ -0,0 +1,14 @@ +/* Check that CONST_INT is not forced into REG before PLUS. */ +/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */ +/* { dg-options "-O2 -fdump-rtl-expand" } */ + +typedef int Arr2[50][50]; + +void +foo (Arr2 a2, int i) +{ + a2[i+20][i] = 1; +} + +/* { dg-final { scan-rtl-dump-not "\\\(set \\\(reg:SI \[0-9\]*\\\)\[\n\r\]+\[ \t]*\\\(const_int 4000" "expand" } } */ +/* { dg-final { cleanup-rtl-dump "expand" } } */ |