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| author | Richard Henderson <rth@redhat.com> | 2011-12-20 16:35:41 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2011-12-20 16:35:41 -0800 |
| commit | 96e69fe20ef229fda89951492305a14c3701262f (patch) | |
| tree | 0afa5581ca85d266dafc9554bd6642d32130adeb /gcc | |
| parent | 6cb2b9646d8daf773d1e8a02c9988dbbc9af1d8c (diff) | |
| download | gcc-96e69fe20ef229fda89951492305a14c3701262f.zip gcc-96e69fe20ef229fda89951492305a14c3701262f.tar.gz gcc-96e69fe20ef229fda89951492305a14c3701262f.tar.bz2 | |
arm: Split xorsi with constant after reload.
This puts xorsi3 in the same format as andsi3 and iorsi3.
This similarity fixes code generation issues with splitting
atomic_fetch_xor post-reload.
* config/arm/arm.md (*arm_xorsi3): Match iorsi3 and perform
post-reload splitting.
From-SVN: r182562
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 24 |
2 files changed, 21 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f5ec754..4304d6e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2011-12-20 Richard Henderson <rth@redhat.com> + * config/arm/arm.md (*arm_xorsi3): Match iorsi3 and perform + post-reload splitting. + * config/arm/arm.md (*arm_cmpdi_unsigned): Enable for thumb2. * config/arm/arm.c (arm_select_cc_mode): Use it. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a5b1df6..751997f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3061,13 +3061,25 @@ }" ) -(define_insn "*arm_xorsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (xor:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "arm_rhs_operand" "rI")))] +(define_insn_and_split "*arm_xorsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r") + (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] "TARGET_32BIT" - "eor%?\\t%0, %1, %2" - [(set_attr "predicable" "yes")] + "@ + eor%?\\t%0, %1, %2 + #" + "TARGET_32BIT + && GET_CODE (operands[2]) == CONST_INT + && !const_ok_for_arm (INTVAL (operands[2]))" + [(clobber (const_int 0))] +{ + arm_split_constant (XOR, SImode, curr_insn, + INTVAL (operands[2]), operands[0], operands[1], 0); + DONE; +} + [(set_attr "length" "4,16") + (set_attr "predicable" "yes")] ) (define_insn "*thumb1_xorsi3_insn" |