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| author | Alexandre Oliva <oliva@adacore.com> | 2022-12-02 21:55:25 -0300 |
|---|---|---|
| committer | Alexandre Oliva <oliva@gnu.org> | 2022-12-02 21:55:25 -0300 |
| commit | 93574914e462e87e42dddd66b0dfbb9627662f33 (patch) | |
| tree | 0a3a7c32a4db6be0d3bf7c42cd5e9d3b34f3060e /gcc | |
| parent | cebd31757800158704d4a301076027df52418773 (diff) | |
| download | gcc-93574914e462e87e42dddd66b0dfbb9627662f33.zip gcc-93574914e462e87e42dddd66b0dfbb9627662f33.tar.gz gcc-93574914e462e87e42dddd66b0dfbb9627662f33.tar.bz2 | |
[testsuite] [riscv] skip ssa-sink-18.c
On riscv64, despite being lp64, we choose two IV candidates as on arm,
which prevents some of the expected sinking. Add an xfail for it.
for gcc/testsuite/ChangeLog
* gcc.dg/tree-ssa/ssa-sink-18.c: xfail sink2 on riscv64.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c index 421c78e..9ac0fc6e 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -207,6 +207,9 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) from bb 31 to bb 33" When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't sink due to ivopts chooses two IV candidates instead of one, which is - expected, so this case is restricted to lp64 only so far. */ + expected, so this case is restricted to lp64 only so far. This different + ivopts choice affects riscv64 as well, probably because it also lacks + base+index addressing modes, so the ip[len] address computation can't be + made from the IV computation above. */ - /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 xfail { riscv64-*-* } } } } */ |