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| author | Luis Machado <luis.machado@linaro.org> | 2017-11-13 10:29:33 +0000 |
|---|---|---|
| committer | Luis Machado <luisgpm@gcc.gnu.org> | 2017-11-13 10:29:33 +0000 |
| commit | 793e17f93b1ad24a86d7a7e25ee34effea4a2689 (patch) | |
| tree | d45461f96e5960d328deafa5e16f06dac484fb41 /gcc | |
| parent | a6fbd15424044457d5c283e5fd2d0d1bb0dcfbb6 (diff) | |
| download | gcc-793e17f93b1ad24a86d7a7e25ee34effea4a2689.zip gcc-793e17f93b1ad24a86d7a7e25ee34effea4a2689.tar.gz gcc-793e17f93b1ad24a86d7a7e25ee34effea4a2689.tar.bz2 | |
[Documentation] Fix latency in pipeline description example
2017-11-09 Luis Machado <luis.machado@linaro.org>
gcc/
* doc/md.texi (Specifying processor pipeline description): Fix
incorrect latency for the div instruction example.
From-SVN: r254680
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 20391e3..c31208a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-11-13 Luis Machado <luis.machado@linaro.org> + + * doc/md.texi (Specifying processor pipeline description): Fix + incorrect latency for the div instruction example. + 2017-11-13 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/78821 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index c4c1138..9806b65 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -9617,7 +9617,7 @@ their result is ready in two cycles. The simple integer insns are issued into the first pipeline unless it is reserved, otherwise they are issued into the second pipeline. Integer division and multiplication insns can be executed only in the second integer -pipeline and their results are ready correspondingly in 8 and 4 +pipeline and their results are ready correspondingly in 9 and 4 cycles. The integer division is not pipelined, i.e.@: the subsequent integer division insn can not be issued until the current division insn finished. Floating point insns are fully pipelined and their @@ -9634,7 +9634,7 @@ incurred. To describe all of this we could specify (define_insn_reservation "mult" 4 (eq_attr "type" "mult") "i1_pipeline, nothing*2, (port0 | port1)") -(define_insn_reservation "div" 8 (eq_attr "type" "div") +(define_insn_reservation "div" 9 (eq_attr "type" "div") "i1_pipeline, div*7, div + (port0 | port1)") (define_insn_reservation "float" 3 (eq_attr "type" "float") |