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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-05-23 10:18:19 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-05-23 10:18:19 +0000 |
| commit | 75c7257f75227e3db09120e38562cf3a3c136ced (patch) | |
| tree | 287bb3cff3821496887f4c3c9e239118156f2c3e /gcc | |
| parent | af6d44b57389b939aa515c177ce35d1e23b2cc07 (diff) | |
| download | gcc-75c7257f75227e3db09120e38562cf3a3c136ced.zip gcc-75c7257f75227e3db09120e38562cf3a3c136ced.tar.gz gcc-75c7257f75227e3db09120e38562cf3a3c136ced.tar.bz2 | |
[AArch64] Fix possible wrong code generation when comparing DImode values.
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_cm<optab>di): Add clobber of CC_REGNUM to unsplit pattern.
From-SVN: r199241
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 42 |
2 files changed, 15 insertions, 32 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b9c78a8..fdfa20c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-05-23 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_cm<optab>di): Add clobber of CC_REGNUM to unsplit pattern. + 2013-05-23 Richard Biener <rguenther@suse.de> PR middle-end/57381 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9069a73..f91cf81 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3280,7 +3280,8 @@ (COMPARISONS:DI (match_operand:DI 1 "register_operand" "w,w,r") (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r") - )))] + ))) + (clobber (reg:CC CC_REGNUM))] "TARGET_SIMD" "@ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2> @@ -3291,15 +3292,7 @@ happening in the 'w' constraint cases. */ && GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))" - [(set (reg:CC CC_REGNUM) - (compare:CC - (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (neg:DI - (COMPARISONS:DI - (match_operand 3 "cc_register" "") - (const_int 0))))] + [(const_int 0)] { enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]); rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); @@ -3332,7 +3325,8 @@ (UCOMPARISONS:DI (match_operand:DI 1 "register_operand" "w,r") (match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r") - )))] + ))) + (clobber (reg:CC CC_REGNUM))] "TARGET_SIMD" "@ cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2> @@ -3342,17 +3336,9 @@ happening in the 'w' constraint cases. */ && GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))" - [(set (reg:CC CC_REGNUM) - (compare:CC - (match_dup 1) - (match_dup 2))) - (set (match_dup 0) - (neg:DI - (UCOMPARISONS:DI - (match_operand 3 "cc_register" "") - (const_int 0))))] + [(const_int 0)] { - enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]); + enum machine_mode mode = CCmode; rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]); emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); @@ -3385,7 +3371,8 @@ (and:DI (match_operand:DI 1 "register_operand" "w,r") (match_operand:DI 2 "register_operand" "w,r")) - (const_int 0))))] + (const_int 0)))) + (clobber (reg:CC CC_REGNUM))] "TARGET_SIMD" "@ cmtst\t%d0, %d1, %d2 @@ -3395,16 +3382,7 @@ happening in the 'w' constraint cases. */ && GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (and:DI (match_dup 1) - (match_dup 2)) - (const_int 0))) - (set (match_dup 0) - (neg:DI - (ne:DI - (match_operand 3 "cc_register" "") - (const_int 0))))] + [(const_int 0)] { rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); |