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| author | Haochen Jiang <haochen.jiang@intel.com> | 2022-05-30 17:12:31 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2022-07-04 14:21:53 +0800 |
| commit | 73f942c08deef3cce312263b3347f7a44dd44150 (patch) | |
| tree | 062ec60619de33306305304148ce32a40bccab90 /gcc | |
| parent | bbe836bc7c557b3f4119e03d24cb61f23906cba9 (diff) | |
| download | gcc-73f942c08deef3cce312263b3347f7a44dd44150.zip gcc-73f942c08deef3cce312263b3347f7a44dd44150.tar.gz gcc-73f942c08deef3cce312263b3347f7a44dd44150.tar.bz2 | |
i386: Extend cvtps2pd to memory
gcc/ChangeLog:
PR target/43618
* config/i386/sse.md (extendv2sfv2df2): New define_expand.
(sse2_cvtps2pd_<mask_name>): Change constraint of operands[1].
(*sse2_cvtps2pd_<mask_name>_1): Rename from extendvsdfv2df2.
gcc/testsuite/ChangeLog:
PR target/43618
* gcc.target/i386/pr43618-1.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 26 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr43618-1.c | 12 |
2 files changed, 33 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f2f72e8..3396ff7 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -9176,11 +9176,27 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_expand "extendv2sfv2df2" + [(set (match_operand:V2DF 0 "register_operand") + (float_extend:V2DF + (match_operand:V2SF 1 "nonimmediate_operand")))] + "TARGET_MMX_WITH_SSE" +{ + if (!MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V4SFmode, + force_reg (V2SFmode, operands[1]), + V2SFmode); + emit_insn (gen_sse2_cvtps2pd (operands[0], operands[1])); + DONE; + } +}) + (define_insn "sse2_cvtps2pd<mask_name>" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "vector_operand" "vm") + (match_operand:V4SF 1 "register_operand" "v") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2 && <mask_avx512vl_condition>" "%vcvtps2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" @@ -9192,12 +9208,12 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2DF")]) -(define_insn "extendv2sfv2df2" +(define_insn "*sse2_cvtps2pd<mask_name>_1" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF - (match_operand:V2SF 1 "register_operand" "v")))] - "TARGET_MMX_WITH_SSE" - "%vcvtps2pd\t{%1, %0|%0, %1}" + (match_operand:V2SF 1 "memory_operand" "m")))] + "TARGET_SSE2 && <mask_avx512vl_condition>" + "%vcvtps2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" [(set_attr "type" "ssecvt") (set_attr "amdfam10_decode" "direct") (set_attr "athlon_decode" "double") diff --git a/gcc/testsuite/gcc.target/i386/pr43618-1.c b/gcc/testsuite/gcc.target/i386/pr43618-1.c new file mode 100644 index 0000000..7d16f0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr43618-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "movq" } } */ +/* { dg-final { scan-assembler "cvtps2pd" } } */ + +void +foo (float a[2], double b[2]) +{ + int i; + for (i = 0; i < 2; i++) + b[i] = a[i]; +} |