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| author | Hongyu Wang <hongyu.wang@intel.com> | 2021-10-15 10:58:16 +0800 |
|---|---|---|
| committer | Hongyu Wang <hongyu.wang@intel.com> | 2021-10-15 12:56:57 +0800 |
| commit | 575191b976a5175be6579590b05f1f1d3550cefc (patch) | |
| tree | 3759213c77ea06a22fbd05196d17e89e96e5efe7 /gcc | |
| parent | f7571527a44808cd7062c77bb9570c13f4f6a126 (diff) | |
| download | gcc-575191b976a5175be6579590b05f1f1d3550cefc.zip gcc-575191b976a5175be6579590b05f1f1d3550cefc.tar.gz gcc-575191b976a5175be6579590b05f1f1d3550cefc.tar.bz2 | |
AVX512FP16: Fix ICE for 2 v4hf vector concat
For V4HFmode, doing vector concat like
__builtin_shufflevector (a, b, {0, 1, 2, 3, 4, 5, 6, 7})
could trigger ICE since it is not handled in ix86_vector_init ().
Handle HFmode like HImode to avoid such ICE.
gcc/ChangeLog:
* config/i386/i386-expand.c (ix86_expand_vector_init):
For half_vector concat for HFmode, handle them like HImode.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512fp16-v4hf-concat.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/i386-expand.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c | 16 |
2 files changed, 18 insertions, 1 deletions
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 9527420..1b01104 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -15122,7 +15122,8 @@ ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals) rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) }; if (inner_mode == QImode || inner_mode == HImode - || inner_mode == TImode) + || inner_mode == TImode + || inner_mode == HFmode) { unsigned int n_bits = n_elts * GET_MODE_SIZE (inner_mode); scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode; diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c new file mode 100644 index 0000000..3b8a7f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vpunpcklqdq" 1 } } */ + +typedef _Float16 v8hf __attribute__((vector_size (16))); +typedef _Float16 v4hf __attribute__((vector_size (8))); + +v8hf foov (v4hf a, v4hf b) +{ + return __builtin_shufflevector (a, b, 0, 1, 2, 3, 4, 5, 6, 7); +} + +v8hf foov2 (v4hf a) +{ + return __builtin_shufflevector (a, (v4hf){0}, 0, 1, 2, 3, 4, 5, 6, 7); +} |