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| author | Tamar Christina <tamar.christina@arm.com> | 2024-06-05 19:31:11 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2024-06-05 19:31:11 +0100 |
| commit | 35f17c680ca650f8658994f857358e5a529c0b93 (patch) | |
| tree | 511a1c7391458205ba5d91d36d7aaf412d3fc71c /gcc | |
| parent | fd4898891ae0c73d6b7aa433cd1ef4539aaa2457 (diff) | |
| download | gcc-35f17c680ca650f8658994f857358e5a529c0b93.zip gcc-35f17c680ca650f8658994f857358e5a529c0b93.tar.gz gcc-35f17c680ca650f8658994f857358e5a529c0b93.tar.bz2 | |
AArch64: add new tuning param and attribute for enabling conditional early clobber
This adds a new tuning parameter AARCH64_EXTRA_TUNE_AVOID_PRED_RMW for AArch64 to
allow us to conditionally enable the early clobber alternatives based on the
tuning models.
gcc/ChangeLog:
* config/aarch64/aarch64-tuning-flags.def
(AVOID_PRED_RMW): New.
* config/aarch64/aarch64.h (TARGET_SVE_PRED_CLOBBER): New.
* config/aarch64/aarch64.md (pred_clobber): New.
(arch_enabled): Use it.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-tuning-flags.def | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.h | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 18 |
3 files changed, 25 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index d5bcaeb..a9f48f5 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -48,4 +48,8 @@ AARCH64_EXTRA_TUNING_OPTION ("avoid_cross_loop_fma", AVOID_CROSS_LOOP_FMA) AARCH64_EXTRA_TUNING_OPTION ("fully_pipelined_fma", FULLY_PIPELINED_FMA) +/* Enable is the target prefers to use a fresh register for predicate outputs + rather than re-use an input predicate register. */ +AARCH64_EXTRA_TUNING_OPTION ("avoid_pred_rmw", AVOID_PRED_RMW) + #undef AARCH64_EXTRA_TUNING_OPTION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index bbf11fa..0997b82 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -495,6 +495,11 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; enabled through +gcs. */ #define TARGET_GCS (AARCH64_ISA_GCS) +/* Prefer different predicate registers for the output of a predicated + operation over re-using an existing input predicate. */ +#define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \ + && (aarch64_tune_params.extra_tuning_flags \ + & AARCH64_EXTRA_TUNE_AVOID_PRED_RMW)) /* Standard register usage. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9dff2d7..389a190 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -445,6 +445,10 @@ ;; target-independent code. (define_attr "is_call" "no,yes" (const_string "no")) +;; Indicates whether we want to enable the pattern with an optional early +;; clobber for SVE predicates. +(define_attr "pred_clobber" "any,no,yes" (const_string "any")) + ;; [For compatibility with Arm in pipeline models] ;; Attribute that specifies whether or not the instruction touches fp ;; registers. @@ -460,7 +464,17 @@ (define_attr "arch_enabled" "no,yes" (if_then_else - (ior + (and + (ior + (and + (eq_attr "pred_clobber" "no") + (match_test "!TARGET_SVE_PRED_CLOBBER")) + (and + (eq_attr "pred_clobber" "yes") + (match_test "TARGET_SVE_PRED_CLOBBER")) + (eq_attr "pred_clobber" "any")) + + (ior (eq_attr "arch" "any") (and (eq_attr "arch" "rcpc8_4") @@ -488,7 +502,7 @@ (match_test "TARGET_SVE")) (and (eq_attr "arch" "sme") - (match_test "TARGET_SME"))) + (match_test "TARGET_SME")))) (const_string "yes") (const_string "no"))) |