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authorAdam Nemet <anemet@caviumnetworks.com>2009-04-19 19:56:14 +0000
committerAdam Nemet <nemet@gcc.gnu.org>2009-04-19 19:56:14 +0000
commit28143fdd2fcabc7d35df8a2e875e684b5c3f7904 (patch)
tree8c998a25227edb784a810d4e7b088e3c90c5825e /gcc
parentda377db901807dd394238b9e01715ce1313af3ef (diff)
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mips.h (mips_tune_attr): New macro.
* config/mips/mips.h (mips_tune_attr): New macro. * config/mips/mips.md (cpu): Use it. From-SVN: r146357
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/mips/mips.h4
-rw-r--r--gcc/config/mips/mips.md2
3 files changed, 10 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 48f1f6c..a7dcc8e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2009-04-19 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/mips/mips.h (mips_tune_attr): New macro.
+ * config/mips/mips.md (cpu): Use it.
+
2009-04-19 Joseph Myers <joseph@codesourcery.com>
PR c/38243
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 6fac454..cd6f1e5 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3463,3 +3463,7 @@ extern enum mips_code_readable_setting mips_code_readable;
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
+
+/* This is necessary to avoid a warning about comparing different enum
+ types. */
+#define mips_tune_attr ((enum attr_cpu) mips_tune)
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 8a67194..8453aab 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -571,7 +571,7 @@
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,r10000,sb1,sb1a,sr71000,xlr"
- (const (symbol_ref "mips_tune")))
+ (const (symbol_ref "mips_tune_attr")))
;; The type of hardware hazard associated with this instruction.
;; DELAY means that the next instruction cannot read the result