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| author | Zhangjin Liao <liaozhangjin@eswincomputing.com> | 2023-08-23 08:02:47 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-23 08:02:47 -0600 |
| commit | 18befd6f050e70f11ecca1dd58624f0ee3c68cc7 (patch) | |
| tree | f6cdfefd653886750d381bf5bcbc723c3b814912 /gcc | |
| parent | 92f2ec417c57e980b92b8966226fc2bfbf042af8 (diff) | |
| download | gcc-18befd6f050e70f11ecca1dd58624f0ee3c68cc7.zip gcc-18befd6f050e70f11ecca1dd58624f0ee3c68cc7.tar.gz gcc-18befd6f050e70f11ecca1dd58624f0ee3c68cc7.tar.bz2 | |
[PATCH] RISC-V:add a more appropriate type attribute
Due to the more accurate type attribute added to the clz, ctz, and pcnt
operations in https://github.com/gcc-mirror/gcc/commit/07e2576d6f3 the
same type attribute should be used here.
gcc/ChangeLog:
* config/riscv/bitmanip.md (*<bitmanip_optab>disi2_sext): Add a more
appropriate type attribute.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0c99152..7b55528 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -262,7 +262,7 @@ (match_operand:DI 2 "const_int_operand")))] "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" "<bitmanip_insn>w\t%0,%1" - [(set_attr "type" "bitmanip") + [(set_attr "type" "<bitmanip_insn>") (set_attr "mode" "SI")]) (define_insn "*<bitmanip_optab>di2" |