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| author | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-05-30 00:16:29 +0000 |
|---|---|---|
| committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2023-05-30 00:16:29 +0000 |
| commit | 187b495acd57e09f7e852b32cada8956dac7d61d (patch) | |
| tree | b994f64ecc93d5c894254540c8f3502346e543e2 /gcc | |
| parent | a1806f0918c0d3612c99b6193b9703d4b4c82c21 (diff) | |
| download | gcc-187b495acd57e09f7e852b32cada8956dac7d61d.zip gcc-187b495acd57e09f7e852b32cada8956dac7d61d.tar.gz gcc-187b495acd57e09f7e852b32cada8956dac7d61d.tar.bz2 | |
Daily bump.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 30 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 10 |
3 files changed, 41 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a7ca6d9..e4a4ed4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,33 @@ +2023-05-29 Die Li <lidie@eswincomputing.com> + + * config/riscv/riscv.cc (riscv_expand_conditional_move_onesided): + Delete. + (riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand + process for TARGET_XTHEADCONDMOV + +2023-05-29 Uros Bizjak <ubizjak@gmail.com> + + PR target/110021 + * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also require + TARGET_AVX512BW to generate truncv16hiv16qi2. + +2023-05-29 Jivan Hakobyan <jivanhakobyan9@gmail.com> + + * config/riscv/riscv.md (and<mode>3): New expander. + (*and<mode>3) New pattern. + * config/riscv/predicates.md (arith_operand_or_mode_mask): New + predicate. + +2023-05-29 Pan Li <pan2.li@intel.com> + + * config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary + comments and rename local variables. + (emit_nonvlmax_insn): Diito. + (emit_vlmax_merge_insn): Ditto. + (emit_vlmax_cmp_insn): Ditto. + (emit_vlmax_cmp_mu_insn): Ditto. + (emit_scalar_move_insn): Ditto. + 2023-05-29 Pan Li <pan2.li@intel.com> * config/riscv/riscv-v.cc (emit_vlmax_insn): Eliminate the diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 5f5439b6..9de50ce 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20230529 +20230530 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 406e6de..281b91c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2023-05-29 Die Li <lidie@eswincomputing.com> + + * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output. + * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise. + +2023-05-29 Jivan Hakobyan <jivanhakobyan9@gmail.com> + + * gcc.target/riscv/and-extend-1.c: New test + * gcc.target/riscv/and-extend-2.c: New test + 2023-05-29 Pan Li <pan2.li@intel.com> * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test. |