s390.md ("*cmp<mode>_ccs_0_ibm", [...]): Insn definitions removed.

2007-04-24  Andreas Krebbel  <krebbel1@de.ibm.com>

	* config/s390/s390.md ("*cmp<mode>_ccs_0_ibm", "*cmp<mode>_ccs_ibm",
	"fix_trunc<BFP:mode><GPR:mode>2_ieee", "fix_truncdfsi2_ibm",
	"floatsidf2_ibm", "floatsisf2", "truncdfsf2_ieee", "truncdfsf2_ibm",
	"*trunctfdf2_ieee", "*trunctfdf2_ibm", "*trunctfsf2_ieee",
	"*trunctfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
	"*extenddftf2_ieee", "*extenddftf2_ibm", "*extendsftf2_ieee",
	"*extendsftf2_ibm", "*add<mode>3", "*add<mode>3_ibm", "*sub<mode>3_ibm",
	"*mul<mode>3", "*mul<mode>3_ibm", "*div<mode>3", "*div<mode>3_ibm",
	"*neg<mode>2_ibm", "*abs<mode>2_ibm"): Insn definitions removed.
	("fix_trunc<BFP:mode><GPR:mode>2_bfp", "floatsi<mode>2",
	"truncdfsf2", "trunctf<mode>2", "add<mode>3", "sub<mode>3",
	"mul<mode>3", "div<mode>3"): Insn definitions added.
	("fixuns_trunc<BFP:mode><GPR:mode>2", "fix_trunc<mode>di2",
	"fix_trunc<mode>si2"): gen_fix_trunc<BFP:mode><GPR:mode>2_ieee renamed
	to gen_fix_trunc<BFP:mode><GPR:mode>2_bfp.
	("fix_truncdfsi2", "floatsitf2", "truncdfsf2", "trunctfdf2",
	"trunctfsf2", "extendsfdf2", "extenddftf2", "extendsftf2", "add<mode>3",
	"sub<mode>3", "mul<mode>3", "div<mode>3"): Expander removed.
	("fix_trunc<mode>si2", "extend<DSF:mode><BFP:mode>2"): Expander added.
	* config/s390/s390.h (TARGET_IBM_FLOAT, TARGET_IEEE_FLOAT,
	TARGET_FLOAT_FORMAT): Macro definitions removed.
	(FP_REGNO_P): No special case for !TARGET_IEEE_FLOAT anymore.
	* config/s390/s390.c (struct processor_costs, z900_cost, z990_cost,
	z9_109_cost): Remove fields for hexfloat instructions: dxr, ddr and der.
	(s390_rtx_costs): Remove !TARGET_IEEE_FLOAT special branches.
	(s390_gen_rtx_const_DI): Function removed.
	* config/s390/s390-protos.h (s390_gen_rtx_const_DI): Prototype removed.

From-SVN: r124097

5 files changed, 103 insertions, 512 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b77b42d..fc6f3bc 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,33 @@
+2007-04-24  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+	* config/s390/s390.md ("*cmp<mode>_ccs_0_ibm", "*cmp<mode>_ccs_ibm",
+	"fix_trunc<BFP:mode><GPR:mode>2_ieee", "fix_truncdfsi2_ibm",
+	"floatsidf2_ibm", "floatsisf2", "truncdfsf2_ieee", "truncdfsf2_ibm",
+	"*trunctfdf2_ieee", "*trunctfdf2_ibm", "*trunctfsf2_ieee",
+	"*trunctfsf2_ibm", "extendsfdf2_ieee", "extendsfdf2_ibm",
+	"*extenddftf2_ieee", "*extenddftf2_ibm", "*extendsftf2_ieee",
+	"*extendsftf2_ibm", "*add<mode>3", "*add<mode>3_ibm", "*sub<mode>3_ibm",
+	"*mul<mode>3", "*mul<mode>3_ibm", "*div<mode>3", "*div<mode>3_ibm",
+	"*neg<mode>2_ibm", "*abs<mode>2_ibm"): Insn definitions removed.
+	("fix_trunc<BFP:mode><GPR:mode>2_bfp", "floatsi<mode>2",
+	"truncdfsf2", "trunctf<mode>2", "add<mode>3", "sub<mode>3",
+	"mul<mode>3", "div<mode>3"): Insn definitions added.
+	("fixuns_trunc<BFP:mode><GPR:mode>2", "fix_trunc<mode>di2",
+	"fix_trunc<mode>si2"): gen_fix_trunc<BFP:mode><GPR:mode>2_ieee renamed
+	to gen_fix_trunc<BFP:mode><GPR:mode>2_bfp.
+	("fix_truncdfsi2", "floatsitf2", "truncdfsf2", "trunctfdf2",
+	"trunctfsf2", "extendsfdf2", "extenddftf2", "extendsftf2", "add<mode>3",
+	"sub<mode>3", "mul<mode>3", "div<mode>3"): Expander removed.
+	("fix_trunc<mode>si2", "extend<DSF:mode><BFP:mode>2"): Expander added.
+	* config/s390/s390.h (TARGET_IBM_FLOAT, TARGET_IEEE_FLOAT,
+	TARGET_FLOAT_FORMAT): Macro definitions removed.
+	(FP_REGNO_P): No special case for !TARGET_IEEE_FLOAT anymore.
+	* config/s390/s390.c (struct processor_costs, z900_cost, z990_cost,
+	z9_109_cost): Remove fields for hexfloat instructions: dxr, ddr and der.
+	(s390_rtx_costs): Remove !TARGET_IEEE_FLOAT special branches.
+	(s390_gen_rtx_const_DI): Function removed.
+	* config/s390/s390-protos.h (s390_gen_rtx_const_DI): Prototype removed.
+
 2007-04-24  Richard Sandiford  <richard@codesourcery.com>
 
 	* optabs.c (set_conv_libfunc): Prefer libgcc2's __ffsMM2 functions
diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 8b2db85..2c86600 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -107,7 +107,6 @@ extern void print_operand (FILE *, rtx, int);
 extern void s390_output_pool_entry (rtx, enum machine_mode, unsigned int);
 extern void s390_trampoline_template (FILE *);
 extern void s390_initialize_trampoline (rtx, rtx, rtx);
-extern rtx s390_gen_rtx_const_DI (int, int);
 extern int s390_agen_dep_p (rtx, rtx);
 extern rtx s390_load_got (void);
 extern rtx s390_get_thread_pointer (void);
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index bd88512..1721971 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -81,11 +81,8 @@ struct processor_costs
   const int maebr;    /* cost of multiply and add in SFmode.  */
   /* division */
   const int dxbr;
-  const int dxr;
   const int ddbr;
-  const int ddr;
   const int debr;
-  const int der;
   const int dlgr;
   const int dlr;
   const int dr;
@@ -118,11 +115,8 @@ struct processor_costs z900_cost =
   COSTS_N_INSNS (18),    /* MADBR */
   COSTS_N_INSNS (13),    /* MAEBR */
   COSTS_N_INSNS (134),   /* DXBR */
-  COSTS_N_INSNS (135),   /* DXR */
   COSTS_N_INSNS (30),    /* DDBR */
-  COSTS_N_INSNS (30),    /* DDR  */
   COSTS_N_INSNS (27),    /* DEBR */
-  COSTS_N_INSNS (26),    /* DER  */
   COSTS_N_INSNS (220),   /* DLGR */
   COSTS_N_INSNS (34),    /* DLR */
   COSTS_N_INSNS (34),    /* DR */
@@ -153,11 +147,8 @@ struct processor_costs z990_cost =
   COSTS_N_INSNS (1),     /* MADBR */
   COSTS_N_INSNS (1),     /* MAEBR */
   COSTS_N_INSNS (60),    /* DXBR */
-  COSTS_N_INSNS (72),    /* DXR */
   COSTS_N_INSNS (40),    /* DDBR */
-  COSTS_N_INSNS (44),    /* DDR  */
-  COSTS_N_INSNS (26),    /* DDBR */
-  COSTS_N_INSNS (28),    /* DER  */
+  COSTS_N_INSNS (26),    /* DEBR */
   COSTS_N_INSNS (176),   /* DLGR */
   COSTS_N_INSNS (31),    /* DLR */
   COSTS_N_INSNS (31),    /* DR */
@@ -188,11 +179,8 @@ struct processor_costs z9_109_cost =
   COSTS_N_INSNS (1),     /* MADBR */
   COSTS_N_INSNS (1),     /* MAEBR */
   COSTS_N_INSNS (60),    /* DXBR */
-  COSTS_N_INSNS (72),    /* DXR */
   COSTS_N_INSNS (40),    /* DDBR */
-  COSTS_N_INSNS (37),    /* DDR  */
-  COSTS_N_INSNS (26),    /* DDBR */
-  COSTS_N_INSNS (28),    /* DER  */
+  COSTS_N_INSNS (26),    /* DEBR */
   COSTS_N_INSNS (30),    /* DLGR */
   COSTS_N_INSNS (23),    /* DLR */
   COSTS_N_INSNS (23),    /* DR */
@@ -2185,7 +2173,7 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total)
       /* Check for multiply and add.  */
       if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode)
 	  && GET_CODE (XEXP (x, 0)) == MULT
-	  && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD)
+	  && TARGET_HARD_FLOAT && TARGET_FUSED_MADD)
 	{
 	  /* This is the multiply and add case.  */
 	  if (GET_MODE (x) == DFmode)
@@ -2292,24 +2280,15 @@ s390_rtx_costs (rtx x, int code, int outer_code, int *total)
 	*total = s390_cost->dlr;
       else if (GET_MODE (x) == SFmode)
 	{
-	  if (TARGET_IEEE_FLOAT)
-	    *total = s390_cost->debr;
-	  else /* TARGET_IBM_FLOAT */
-	    *total = s390_cost->der;
+	  *total = s390_cost->debr;
 	}
       else if (GET_MODE (x) == DFmode)
 	{
-	  if (TARGET_IEEE_FLOAT)
-	    *total = s390_cost->ddbr;
-	  else /* TARGET_IBM_FLOAT */
-	    *total = s390_cost->ddr;
+	  *total = s390_cost->ddbr;
 	}
       else if (GET_MODE (x) == TFmode)
 	{
-	  if (TARGET_IEEE_FLOAT)
-	    *total = s390_cost->dxbr;
-	  else /* TARGET_IBM_FLOAT */
-	    *total = s390_cost->dxr;
+	  *total = s390_cost->dxbr;
 	}
       return false;
 
@@ -8389,28 +8368,6 @@ s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
 		   plus_constant (addr, (TARGET_64BIT ? 24 : 12)))), fnaddr);
 }
 
-/* Return rtx for 64-bit constant formed from the 32-bit subwords
-   LOW and HIGH, independent of the host word size.  */
-
-rtx
-s390_gen_rtx_const_DI (int high, int low)
-{
-#if HOST_BITS_PER_WIDE_INT >= 64
-  HOST_WIDE_INT val;
-  val = (HOST_WIDE_INT)high;
-  val <<= 32;
-  val |= (HOST_WIDE_INT)low;
-
-  return GEN_INT (val);
-#else
-#if HOST_BITS_PER_WIDE_INT >= 32
-  return immed_double_const ((HOST_WIDE_INT)low, (HOST_WIDE_INT)high, DImode);
-#else
-  gcc_unreachable ();
-#endif
-#endif
-}
-
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  */
 
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 8f004a3..f95dae2 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -103,10 +103,6 @@ extern enum processor_flags s390_arch_flags;
     }							\
   while (0)
 
-/* ??? Once this actually works, it could be made a runtime option.  */
-#define TARGET_IBM_FLOAT           0
-#define TARGET_IEEE_FLOAT          1
-
 #ifdef DEFAULT_TARGET_64BIT
 #define TARGET_DEFAULT             (MASK_64BIT | MASK_ZARCH)
 #else
@@ -225,10 +221,6 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
   (LEVEL == SAVE_FUNCTION ? VOIDmode    \
   : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode)
 
-/* Define target floating point format.  */
-#define TARGET_FLOAT_FORMAT \
-  (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT)
-
 
 /* Type layout.  */
 
@@ -285,7 +277,7 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
 /* Standard register usage.  */
 #define GENERAL_REGNO_P(N)	((int)(N) >= 0 && (N) < 16)
 #define ADDR_REGNO_P(N)		((N) >= 1 && (N) < 16)
-#define FP_REGNO_P(N)		((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20))
+#define FP_REGNO_P(N)		((N) >= 16 && (N) < 32)
 #define CC_REGNO_P(N)		((N) == 33)
 #define FRAME_REGNO_P(N)	((N) == 32 || (N) == 34 || (N) == 35)
 #define ACCESS_REGNO_P(N)	((N) == 36 || (N) == 37)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 4acba12..4190535 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -796,46 +796,23 @@
   [(set (reg CC_REGNUM)
         (compare (match_operand:FP 0 "register_operand" "f")
                  (match_operand:FP 1 "const0_operand"   "")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
   "lt<xde><bt>r\t%0,%0"
    [(set_attr "op_type" "RRE")
     (set_attr "type"  "fsimp<bfp>")])
 
-; ltxr, ltdr, lter
-(define_insn "*cmp<mode>_ccs_0_ibm"
-  [(set (reg CC_REGNUM)
-        (compare (match_operand:BFP 0 "register_operand" "f")
-                 (match_operand:BFP 1 "const0_operand" "")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lt<xde>r\t%0,%0"
-   [(set_attr "op_type" "<RRe>")
-    (set_attr "type"  "fsimp<mode>")])
-
 ; cxtr, cxbr, cdbr, cebr, cxb, cdb, ceb, cxbtr, cdbtr
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
         (compare (match_operand:FP 0 "register_operand" "f,f")
                  (match_operand:FP 1 "general_operand"  "f,<Rf>")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    c<xde><bt>r\t%0,%1
    c<xde>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
     (set_attr "type"  "fsimp<bfp>")])
 
-; cxr, cdr, cer, cx, cd, ce
-(define_insn "*cmp<mode>_ccs_ibm"
-  [(set (reg CC_REGNUM)
-        (compare (match_operand:BFP 0 "register_operand" "f,f")
-                 (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   c<xde>r\t%0,%1
-   c<xde>\t%0,%1"
-   [(set_attr "op_type" "<RRe>,<RXe>")
-    (set_attr "type"  "fsimp<mode>")])
-
-
 ;;
 ;;- Move instructions.
 ;;
@@ -2304,7 +2281,7 @@
                      UNSPEC_TDC_INSN))
    (set (match_operand:SI 0 "register_operand" "=d")
         (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
 {
   operands[2] = GEN_INT (S390_TDC_INFINITY);
 })
@@ -2318,7 +2295,7 @@
   [(set (reg:CCZ CC_REGNUM)
         (unspec:CCZ [(match_operand:BFP 0 "register_operand" "f") 
                      (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "tc<xde>b\t%0,%1"
    [(set_attr "op_type" "RXE")
     (set_attr "type"  "fsimp<mode>")])
@@ -3265,7 +3242,7 @@
 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
   [(set (match_operand:GPR 0 "register_operand" "")
         (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
@@ -3281,12 +3258,12 @@
   emit_jump_insn (gen_blt (label1));
   emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
-  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0], temp,
+  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
 	GEN_INT (7)));
   emit_jump (label2);
 
   emit_label (label1);
-  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0],
+  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
 	operands[1], GEN_INT (5)));
   emit_label (label2);
   DONE;
@@ -3295,21 +3272,21 @@
 (define_expand "fix_trunc<mode>di2"
   [(set (match_operand:DI 0 "register_operand" "")
         (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_64BIT && TARGET_HARD_FLOAT"
 {
   operands[1] = force_reg (<MODE>mode, operands[1]);
-  emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1],
+  emit_insn (gen_fix_trunc<mode>di2_bfp (operands[0], operands[1],
       GEN_INT (5)));
   DONE;
 })
 
 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
-(define_insn "fix_trunc<BFP:mode><GPR:mode>2_ieee"
+(define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
   [(set (match_operand:GPR 0 "register_operand" "=d")
         (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
    (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "ftoi")])
@@ -3351,254 +3328,72 @@
 		   (fix:GPR (match_operand:TF 1 "register_operand" "")))
 	      (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
 	      (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "")
-
-;
-; fix_truncdfsi2 instruction pattern(s).
-;
-
-(define_expand "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
   "TARGET_HARD_FLOAT"
-{
-  if (TARGET_IBM_FLOAT)
-    {
-      /* This is the algorithm from POP chapter A.5.7.2.  */
-
-      rtx temp   = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
-      rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
-      rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
-
-      operands[1] = force_reg (DFmode, operands[1]);
-      emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
-					 two31r, two32, temp));
-    }
-  else
-    {
-      operands[1] = force_reg (DFmode, operands[1]);
-      emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
-    }
-
-  DONE;
-})
-
-(define_insn "fix_truncdfsi2_ibm"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
-   (use (match_operand:DI 2 "immediate_operand" "m"))
-   (use (match_operand:DI 3 "immediate_operand" "m"))
-   (use (match_operand:BLK 4 "memory_operand" "m"))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-{
-   output_asm_insn ("sd\t%1,%2", operands);
-   output_asm_insn ("aw\t%1,%3", operands);
-   output_asm_insn ("std\t%1,%4", operands);
-   output_asm_insn ("xi\t%N4,128", operands);
-   return "l\t%0,%N4";
-}
-  [(set_attr "length" "20")])
+  "")
 
 ;
-; fix_truncsfsi2 instruction pattern(s).
+; fix_trunc(df|sf)si2 instruction pattern(s).
 ;
 
-(define_expand "fix_truncsfsi2"
+(define_expand "fix_trunc<mode>si2"
   [(set (match_operand:SI 0 "register_operand" "")
-        (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
+        (fix:SI (match_operand:DSF 1 "nonimmediate_operand" "")))]
   "TARGET_HARD_FLOAT"
 {
-  if (TARGET_IBM_FLOAT)
-    {
-      /* Convert to DFmode and then use the POP algorithm.  */
-      rtx temp = gen_reg_rtx (DFmode);
-      emit_insn (gen_extendsfdf2 (temp, operands[1]));
-      emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
-    }
-  else
-    {
-      operands[1] = force_reg (SFmode, operands[1]);
-      emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
-    }
-
+  operands[1] = force_reg (<MODE>mode, operands[1]);
+  emit_insn (gen_fix_trunc<mode>si2_bfp (operands[0], operands[1], GEN_INT (5)));
   DONE;
 })
 
 ;
-; float(si|di)(tf|df|sf)2 instruction pattern(s).
+; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
 ;
 
 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
 (define_insn "floatdi<mode>2"
   [(set (match_operand:FP 0 "register_operand" "=f")
         (float:FP (match_operand:DI 1 "register_operand" "d")))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_64BIT && TARGET_HARD_FLOAT"
   "c<xde>g<bt>r\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "itof" )])
 
 ; cxfbr, cdfbr, cefbr
-(define_insn "floatsi<mode>2_ieee"
+(define_insn "floatsi<mode>2"
   [(set (match_operand:BFP 0 "register_operand" "=f")
         (float:BFP (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "c<xde>fbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"   "itof" )])
 
 
 ;
-; floatsi(tf|df)2 instruction pattern(s).
-;
-
-(define_expand "floatsitf2"
-  [(set (match_operand:TF 0 "register_operand" "")
-        (float:TF (match_operand:SI 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "")
-
-(define_expand "floatsidf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-        (float:DF (match_operand:SI 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT"
-{
-  if (TARGET_IBM_FLOAT)
-    {
-      /* This is the algorithm from POP chapter A.5.7.1.  */
-
-      rtx temp  = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
-      rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
-
-      emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
-      DONE;
-    }
-})
-
-(define_insn "floatsidf2_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (float:DF (match_operand:SI 1 "register_operand" "d")))
-   (use (match_operand:DI 2 "immediate_operand" "m"))
-   (use (match_operand:BLK 3 "memory_operand" "m"))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-{
-   output_asm_insn ("st\t%1,%N3", operands);
-   output_asm_insn ("xi\t%N3,128", operands);
-   output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
-   output_asm_insn ("ld\t%0,%3", operands);
-   return "sd\t%0,%2";
-}
-  [(set_attr "length" "20")])
-
-;
-; floatsisf2 instruction pattern(s).
-;
-
-(define_expand "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (float:SF (match_operand:SI 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT"
-{
-  if (TARGET_IBM_FLOAT)
-    {
-      /* Use the POP algorithm to convert to DFmode and then truncate.  */
-      rtx temp = gen_reg_rtx (DFmode);
-      emit_insn (gen_floatsidf2 (temp, operands[1]));
-      emit_insn (gen_truncdfsf2 (operands[0], temp));
-      DONE;
-    }
-})
-
-;
 ; truncdfsf2 instruction pattern(s).
 ;
 
-(define_expand "truncdfsf2"
-  [(set (match_operand:SF 0 "register_operand" "")
-        (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "truncdfsf2_ieee"
+(define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
         (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "ledbr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"   "ftruncdf")])
 
-(define_insn "truncdfsf2_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   ler\t%0,%1
-   le\t%0,%1"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"   "floadsf")])
-
 ;
-; trunctfdf2 instruction pattern(s).
+; trunctf(df|sf)2 instruction pattern(s).
 ;
 
-(define_expand "trunctfdf2"
-  [(parallel 
-    [(set (match_operand:DF 0 "register_operand" "")
-	  (float_truncate:DF (match_operand:TF 1 "register_operand" "")))
-     (clobber (match_scratch:TF 2 "=f"))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*trunctfdf2_ieee"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
+; ldxbr, lexbr
+(define_insn "trunctf<mode>2"
+  [(set (match_operand:DSF 0 "register_operand" "=f")
+        (float_truncate:DSF (match_operand:TF 1 "register_operand" "f")))
    (clobber (match_scratch:TF 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ldxbr\t%2,%1\;ldr\t%0,%2"
+  "TARGET_HARD_FLOAT"
+  "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2"
   [(set_attr "length" "6")
    (set_attr "type"   "ftrunctf")])   
 
-(define_insn "*trunctfdf2_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (float_truncate:DF (match_operand:TF 1 "register_operand" "f")))
-   (clobber (match_scratch:TF 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "ldxr\t%2,%1\;ldr\t%0,%2"
-  [(set_attr "length"  "4")
-   (set_attr "type"   "ftrunctf")])
-
-;
-; trunctfsf2 instruction pattern(s).
-;
-
-(define_expand "trunctfsf2"
-  [(parallel 
-    [(set (match_operand:SF 0 "register_operand" "=f")
-	  (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
-     (clobber (match_scratch:TF 2 "=f"))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*trunctfsf2_ieee"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
-   (clobber (match_scratch:TF 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lexbr\t%2,%1\;ler\t%0,%2"
-  [(set_attr "length"  "6")
-   (set_attr "type"   "ftrunctf")])
-
-(define_insn "*trunctfsf2_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (float_truncate:SF (match_operand:TF 1 "register_operand" "f")))
-   (clobber (match_scratch:TF 2 "=f"))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lexr\t%2,%1\;ler\t%0,%2"
-  [(set_attr "length"  "6")
-   (set_attr "type"   "ftrunctf")])
-
 ;
 ; trunctddd2 and truncddsd2 instruction pattern(s).
 ;
@@ -3621,101 +3416,20 @@
    (set_attr "type"    "fsimptf")])
 
 ;
-; extendsfdf2 instruction pattern(s).
-;
-
-(define_expand "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "")
-        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_HARD_FLOAT"
-{
-  if (TARGET_IBM_FLOAT)
-    {
-      emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
-      DONE;
-    }
-})
-
-(define_insn "extendsfdf2_ieee"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   ldebr\t%0,%1
-   ldeb\t%0,%1"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"   "fsimpsf, floadsf")])
-
-(define_insn "extendsfdf2_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   sdr\t%0,%0\;ler\t%0,%1
-   sdr\t%0,%0\;le\t%0,%1"
-  [(set_attr "length"   "4,6")
-   (set_attr "type"     "floadsf")])
-
-;
-; extenddftf2 instruction pattern(s).
+; extend(sf|df)(df|tf)2 instruction pattern(s).
 ;
 
-(define_expand "extenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "")
-        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*extenddftf2_ieee"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   lxdbr\t%0,%1
-   lxdb\t%0,%1"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"   "fsimptf, floadtf")])
-
-(define_insn "*extenddftf2_ibm"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-        (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   lxdr\t%0,%1
-   lxd\t%0,%1"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"   "fsimptf, floadtf")])
-
-;
-; extendsftf2 instruction pattern(s).
-;
-
-(define_expand "extendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "")
-        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*extendsftf2_ieee"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   lxebr\t%0,%1
-   lxeb\t%0,%1"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"   "fsimptf, floadtf")])
-
-(define_insn "*extendsftf2_ibm"
-  [(set (match_operand:TF 0 "register_operand" "=f,f")
-        (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
+; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
+(define_insn "extend<DSF:mode><BFP:mode>2"
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand"  "f,R")))]
+  "TARGET_HARD_FLOAT
+   && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
   "@
-   lxer\t%0,%1
-   lxe\t%0,%1"
+   l<BFP:xde><DSF:xde>br\t%0,%1
+   l<BFP:xde><DSF:xde>b\t%0,%1"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"   "fsimptf, floadtf")])
+   (set_attr "type"   "fsimp<BFP:mode>, fload<BFP:mode>")])
 
 ;
 ; extendddtd2 and extendsddd2 instruction pattern(s).
@@ -4063,22 +3777,13 @@
 ; add(tf|df|sf|td|dd)3 instruction pattern(s).
 ;
 
-(define_expand "add<mode>3"
-  [(parallel
-    [(set (match_operand:FP 0 "register_operand" "")
-          (plus:FP (match_operand:FP 1 "nonimmediate_operand" "")
-                    (match_operand:FP 2 "general_operand" "")))
-     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
-(define_insn "*add<mode>3"
+(define_insn "add<mode>3"
   [(set (match_operand:FP 0 "register_operand"              "=f,   f")
         (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
 		 (match_operand:FP 2 "general_operand"      " f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
@@ -4093,7 +3798,7 @@
 		 (match_operand:FP 3 "const0_operand" "")))
    (set (match_operand:FP 0 "register_operand" "=f,f")
 	(plus:FP (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
@@ -4107,26 +3812,13 @@
 			   (match_operand:FP 2 "general_operand"      " f,<Rf>"))
 		 (match_operand:FP 3 "const0_operand" "")))
    (clobber (match_scratch:FP 0 "=f,f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    a<xde><bt>r\t%0,<op1>%2
    a<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
    (set_attr "type"     "fsimp<bfp>")])
 
-; axr, adr, aer, ax, ad, ae
-(define_insn "*add<mode>3_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f,f")
-        (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   a<xde>r\t%0,%2
-   a<xde>\t%0,%2"
-  [(set_attr "op_type"  "<RRe>,<RXe>")
-   (set_attr "type"     "fsimp<mode>")])
-
 
 ;;
 ;;- Subtract instructions.
@@ -4406,22 +4098,13 @@
 ; sub(tf|df|sf|td|dd)3 instruction pattern(s).
 ;
 
-(define_expand "sub<mode>3"
-  [(parallel
-    [(set (match_operand:FP 0 "register_operand" "")
-          (minus:FP (match_operand:FP 1 "register_operand" "")
-                     (match_operand:FP 2 "general_operand" "")))
-     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
 ; sxbr, sdbr, sebr, sxb, sdb, seb, sxtr, sdtr
-(define_insn "*sub<mode>3"
+(define_insn "sub<mode>3"
   [(set (match_operand:FP 0 "register_operand"            "=f,  f")
         (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
-                   (match_operand:FP 2 "general_operand"  "f,<Rf>")))
+                  (match_operand:FP 2 "general_operand"  "f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
@@ -4432,11 +4115,11 @@
 (define_insn "*sub<mode>3_cc"
   [(set (reg CC_REGNUM)
 	(compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
-			    (match_operand:FP 2 "general_operand"      "f,<Rf>"))
+                           (match_operand:FP 2 "general_operand"      "f,<Rf>"))
 		 (match_operand:FP 3 "const0_operand" "")))
    (set (match_operand:FP 0 "register_operand" "=f,f")
 	(minus:FP (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
@@ -4450,26 +4133,13 @@
 			   (match_operand:FP 2 "general_operand"      "f,<Rf>"))
 		 (match_operand:FP 3 "const0_operand" "")))
    (clobber (match_scratch:FP 0 "=f,f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "@
    s<xde><bt>r\t%0,<op1>%2
    s<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
    (set_attr "type"     "fsimp<bfp>")])
 
-; sxr, sdr, ser, sx, sd, se
-(define_insn "*sub<mode>3_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f,f")
-        (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
-                   (match_operand:BFP 2 "general_operand" "f,<Rf>")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   s<xde>r\t%0,%2
-   s<xde>\t%0,%2"
-  [(set_attr "op_type"  "<RRe>,<RXe>")
-   (set_attr "type"     "fsimp<mode>")])
-
 
 ;;
 ;;- Conditional add/subtract instructions.
@@ -4716,44 +4386,25 @@
 ; mul(tf|df|sf|td|dd)3 instruction pattern(s).
 ;
 
-(define_expand "mul<mode>3"
-  [(set (match_operand:FP 0 "register_operand" "")
-        (mult:FP (match_operand:FP 1 "nonimmediate_operand" "")
-                  (match_operand:FP 2 "general_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
 ; mxbr mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
-(define_insn "*mul<mode>3"
+(define_insn "mul<mode>3"
   [(set (match_operand:FP 0 "register_operand"              "=f,f")
         (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
                  (match_operand:FP 2 "general_operand"      "f,<Rf>")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "@
    m<xdee><bt>r\t%0,<op1>%2
    m<xdee>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
    (set_attr "type"     "fmul<bfp>")])
 
-; mxr, mdr, mer, mx, md, me
-(define_insn "*mul<mode>3_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f,f")
-        (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   m<xde>r\t%0,%2
-   m<xde>\t%0,%2"
-  [(set_attr "op_type"  "<RRe>,<RXe>")
-   (set_attr "type"     "fmul<mode>")])
-
 ; maxbr, madbr, maebr, maxb, madb, maeb
 (define_insn "*fmadd<mode>"
   [(set (match_operand:DSF 0 "register_operand" "=f,f")
 	(plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f")
 			    (match_operand:DSF 2 "nonimmediate_operand"  "f,R"))
 		 (match_operand:DSF 3 "register_operand" "0,0")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
   "@
    ma<xde>br\t%0,%1,%2
    ma<xde>b\t%0,%1,%2"
@@ -4766,7 +4417,7 @@
 	(minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f")
 			     (match_operand:DSF 2 "nonimmediate_operand"  "f,R"))
 		 (match_operand:DSF 3 "register_operand" "0,0")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+  "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
   "@
    ms<xde>br\t%0,%1,%2
    ms<xde>b\t%0,%1,%2"
@@ -5195,37 +4846,18 @@
 ; div(df|sf)3 instruction pattern(s).
 ;
 
-(define_expand "div<mode>3"
-  [(set (match_operand:FP 0 "register_operand" "")
-        (div:FP (match_operand:FP 1 "register_operand" "")
-                 (match_operand:FP 2 "general_operand" "")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
-(define_insn "*div<mode>3"
+(define_insn "div<mode>3"
   [(set (match_operand:FP 0 "register_operand"          "=f,f")
         (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
                  (match_operand:FP 2 "general_operand"  "f,<Rf>")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "@
    d<xde><bt>r\t%0,<op1>%2
    d<xde>b\t%0,%2"
   [(set_attr "op_type"  "<RRer>,RXE")
    (set_attr "type"     "fdiv<bfp>")])
 
-; dxr, ddr, der, dx, dd, de
-(define_insn "*div<mode>3_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f,f")
-        (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
-                 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   d<xde>r\t%0,%2
-   d<xde>\t%0,%2"
-  [(set_attr "op_type"  "<RRe>,<RXe>")
-   (set_attr "type"     "fdiv<mode>")])
-
 
 ;;
 ;;- And instructions.
@@ -6209,7 +5841,7 @@
                  (match_operand:BFP 2 "const0_operand" "")))
    (set (match_operand:BFP 0 "register_operand" "=f")
         (neg:BFP (match_dup 1)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "lc<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6220,7 +5852,7 @@
         (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
                  (match_operand:BFP 2 "const0_operand" "")))
    (clobber (match_scratch:BFP 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "lc<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6239,21 +5871,11 @@
   [(set (match_operand:BFP 0 "register_operand" "=f")
         (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "lc<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
 
-; lcxr, lcdr, lcer
-(define_insn "*neg<mode>2_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f")
-        (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lc<xde>r\t%0,%1"
-  [(set_attr "op_type"  "<RRe>")
-   (set_attr "type"     "fsimp<mode>")])
-
 
 ;;
 ;;- Absolute value instructions.
@@ -6332,7 +5954,7 @@
                  (match_operand:BFP 2 "const0_operand" "")))
    (set (match_operand:BFP 0 "register_operand" "=f")
         (abs:BFP (match_dup 1)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "lp<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6343,7 +5965,7 @@
         (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
                  (match_operand:BFP 2 "const0_operand" "")))
    (clobber (match_scratch:BFP 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "lp<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6362,20 +5984,11 @@
   [(set (match_operand:BFP 0 "register_operand" "=f")
         (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "lp<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
 
-; lpxr, lpdr, lper
-(define_insn "*abs<mode>2_ibm"
-  [(set (match_operand:BFP 0 "register_operand" "=f")
-        (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
-   (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lp<xde>r\t%0,%1"
-  [(set_attr "op_type"  "<RRe>")
-   (set_attr "type"     "fsimp<mode>")])
 
 ;;
 ;;- Negated absolute value instructions
@@ -6447,7 +6060,7 @@
                  (match_operand:BFP 2 "const0_operand" "")))
    (set (match_operand:BFP 0 "register_operand" "=f")
         (neg:BFP (abs:BFP (match_dup 1))))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "ln<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6458,7 +6071,7 @@
         (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
                  (match_operand:BFP 2 "const0_operand" "")))
    (clobber (match_scratch:BFP 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
   "ln<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6477,7 +6090,7 @@
   [(set (match_operand:BFP 0 "register_operand" "=f")
         (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "ln<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimp<mode>")])
@@ -6509,7 +6122,7 @@
 (define_insn "sqrt<mode>2"
   [(set (match_operand:BFP 0 "register_operand" "=f,f")
 	(sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "TARGET_HARD_FLOAT"
   "@
    sq<xde>br\t%0,%1
    sq<xde>b\t%0,%1"