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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-01-13 08:45:59 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2013-01-13 08:45:59 +0000 |
| commit | 140516c568165e2cb46d8b07cb78681ee1975172 (patch) | |
| tree | e39fc00752f7141046de78ae09727a4316844ac1 /gcc | |
| parent | fbd03a27c7d0201e34d22dd90be3ad65e8df8569 (diff) | |
| download | gcc-140516c568165e2cb46d8b07cb78681ee1975172.zip gcc-140516c568165e2cb46d8b07cb78681ee1975172.tar.gz gcc-140516c568165e2cb46d8b07cb78681ee1975172.tar.bz2 | |
ssa-dom-thread-4.c: Update expected results for MIPS.
gcc/testsuite/
* gcc.dg/tree-ssa/ssa-dom-thread-4.c: Update expected results for MIPS.
From-SVN: r195131
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c | 23 |
2 files changed, 24 insertions, 3 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f847f1b..e4117fb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2013-01-13 Richard Sandiford <rdsandiford@googlemail.com> + + * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Update expected results for MIPS. + 2013-01-12 Janus Weil <janus@gcc.gnu.org> PR fortran/55072 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c index 1cf3f0b..44b05f0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c @@ -62,8 +62,25 @@ bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b, /* ARM Cortex-M0 defined LOGICAL_OP_NON_SHORT_CIRCUIT to false, so skip below test. */ /* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { mips*-*-* || { arm_cortex_m && arm_thumb1 } } } } } } */ -/* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split var1 || var2 - into two conditions, rather than use (var1 != 0) | (var2 != 0). */ -/* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target mips*-*-* } } } */ +/* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split both + "a_elt || b_elt" and "b_elt && kill_elt" into two conditions each, + rather than using "(var1 != 0) op (var2 != 0)". Also, as on other targets, + we duplicate the header of the inner "while" loop. There are then + 6 threading opportunities: + + 1x "!a_elt && b_elt" in the outer "while" loop + -> the start of the inner "while" loop, + skipping the known-true "b_elt" in the first condition. + 1x "!b_elt" in the first condition + -> the outer "while" loop's continuation point, + skipping the known-false "b_elt" in the second condition. + 2x "!kill_elt" in the inner "while" loop + -> the outer "while" loop's continuation point, + skipping the known-false "b_elt && kill_elt" in the second condition + 2x "kill_elt->indx < b_elt->indx" in the first "while" loop + -> "kill_elt->indx == b_elt->indx" in the second condition, + skipping the known-true "b_elt && kill_elt" in the second + condition. */ +/* { dg-final { scan-tree-dump-times "Threaded" 6 "dom1" { target mips*-*-* } } } */ /* { dg-final { cleanup-tree-dump "dom1" } } */ |