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| author | Tamar Christina <tamar.christina@arm.com> | 2022-08-12 12:28:41 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2022-08-12 12:28:41 +0100 |
| commit | f4ff20d464f90c85919ce2e7fa63e204dcda4e40 (patch) | |
| tree | 179246fd5aa1757653a451341bcea38cdf3d0198 /gcc | |
| parent | 7e3b45befdbbf1a1f9ff728fa2bac31b4756907c (diff) | |
| download | gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.zip gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.tar.gz gcc-f4ff20d464f90c85919ce2e7fa63e204dcda4e40.tar.bz2 | |
sve: Fix fcmuo combine patterns [PR106524]
There's no encoding for fcmuo with zero. This restricts the combine patterns
from accepting zero registers.
gcc/ChangeLog:
PR target/106524
* config/aarch64/aarch64-sve.md (*fcmuo<mode>_nor_combine,
*fcmuo<mode>_bic_combine): Don't accept comparisons against zero.
gcc/testsuite/ChangeLog:
PR target/106524
* gcc.target/aarch64/sve/pr106524.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/pr106524.c | 11 |
2 files changed, 13 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index bd60e65..e08bee1 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8231,7 +8231,7 @@ [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (match_operand:<VPRED> 4 "register_operand" "Upa")) (match_dup:<VPRED> 1))) @@ -8267,7 +8267,7 @@ [(match_operand:<VPRED> 1) (const_int SVE_KNOWN_PTRUE) (match_operand:SVE_FULL_F 2 "register_operand" "w") - (match_operand:SVE_FULL_F 3 "aarch64_simd_reg_or_zero" "wDz")] + (match_operand:SVE_FULL_F 3 "register_operand" "w")] UNSPEC_COND_FCMUO)) (not:<VPRED> (match_operand:<VPRED> 4 "register_operand" "Upa"))) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c new file mode 100644 index 0000000..a9f650f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr106524.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+sve -O2 -fno-move-loop-invariants" } */ + +void +test__zero (int *restrict dest, int *restrict src, float *a, int count) +{ + int i; + + for (i = 0; i < count; ++i) + dest[i] = !__builtin_isunordered (a[i], 0) ? src[i] : 0; +} |