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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:06:45 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-08-25 07:06:45 -0600 |
| commit | ab9c4bb54e817948f1a55edfb0f1f0481e4046df (patch) | |
| tree | a029e16c675ce0be4bf15f9ecdddb7e68cc6602b /gcc | |
| parent | 91f549537caa8dff2621c22ef2cdd48c55b0ad19 (diff) | |
| download | gcc-ab9c4bb54e817948f1a55edfb0f1f0481e4046df.zip gcc-ab9c4bb54e817948f1a55edfb0f1f0481e4046df.tar.gz gcc-ab9c4bb54e817948f1a55edfb0f1f0481e4046df.tar.bz2 | |
Turn off late-combine for a few risc-v specific tests
Just minor testsuite adjustments -- several of the shorten-memref tests are
slightly twiddled by the late-combine pass:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ...
> FAIL: gcc.target/riscv/shorten-memrefs-2.c -Os scan-assembler store1a:\n(\t?\\.[^\n]*\n)*\taddi
> XPASS: gcc.target/riscv/shorten-memrefs-3.c -Os scan-assembler-not load2a:\n.*addi[ \t]*[at][0-9],[at][0-9],[0-9]*
> FAIL: gcc.target/riscv/shorten-memrefs-5.c -Os scan-assembler store1a:\n(\t?\\.[^\n]*\n)*\taddi
> FAIL: gcc.target/riscv/shorten-memrefs-8.c -Os scan-assembler store:\n(\t?\\.[^\n]*\n)*\taddi\ta[0-7],a[0-7],1
This patch just turns off the late-combine pass for those tests. Locally I'd
adjusted all the shorten-memref patches, but a quick re-rest shows that only 4
tests seem affected right now.
Anyway, pushing to the trunk to slightly clean up our test results.
gcc/testsuite
* gcc.target/riscv/shorten-memrefs-2.c: Turn off late-combine.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
Diffstat (limited to 'gcc')
4 files changed, 4 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c index a9ddb79..29ece48 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c @@ -1,4 +1,4 @@ -/* { dg-options "-march=rv32imc -mabi=ilp32" } */ +/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" } */ /* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */ /* shorten_memrefs should rewrite these load/stores into a compressible diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c index 3d56112..273a68c 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c @@ -1,4 +1,4 @@ -/* { dg-options "-march=rv32imc -mabi=ilp32" } */ +/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" } */ /* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */ /* These loads cannot be compressed because only one compressed reg is diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c index 11e858e..f554105 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c @@ -1,4 +1,4 @@ -/* { dg-options "-march=rv64imc -mabi=lp64" } */ +/* { dg-options "-march=rv64imc -mabi=lp64 -fno-late-combine-instructions" } */ /* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */ /* shorten_memrefs should rewrite these load/stores into a compressible diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c index 3ff6956..d533355 100644 --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c @@ -1,4 +1,4 @@ -/* { dg-options "-march=rv32imc -mabi=ilp32" } */ +/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" } */ /* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */ /* shorten_memrefs should use a correct base address*/ |