i386.c (ix86_decompose_address): Use lowpart_subreg instead of simplify_gen_subreg (...

	* config/i386/i386.c (ix86_decompose_address): Use lowpart_subreg
	instead of simplify_gen_subreg (... , 0).
	(ix86_delegitimize_address): Ditto.
	(ix86_split_divmod): Ditto.
	(ix86_split_copysign_const): Ditto.
	(ix86_split_copysign_var): Ditto.
	(ix86_expand_args_builtin): Ditto.
	(ix86_expand_round_builtin): Ditto.
	(ix86_expand_special_args_builtin): Ditto.
	* config/i386/i386.md (TARGET_USE_VECTOR_FP_CONVERTS splitters): Ditto.
	(TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters and peephole2s): Ditto.
	(udivmodqi4): Ditto.
	(absneg splitters): Ditto.
	(*jcc_bt<mode>_1): Ditto.

From-SVN: r235207

3 files changed, 58 insertions, 48 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6c338f7..095d1d4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2016-04-19  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.c (ix86_decompose_address): Use lowpart_subreg
+	instead of simplify_gen_subreg (... , 0).
+	(ix86_delegitimize_address): Ditto.
+	(ix86_split_divmod): Ditto.
+	(ix86_split_copysign_const): Ditto.
+	(ix86_split_copysign_var): Ditto.
+	(ix86_expand_args_builtin): Ditto.
+	(ix86_expand_round_builtin): Ditto.
+	(ix86_expand_special_args_builtin): Ditto.
+	* config/i386/i386.md (TARGET_USE_VECTOR_FP_CONVERTS splitters): Ditto.
+	(TARGET_SSE_PARTIAL_REG_DEPENDENCY splitters and peephole2s): Ditto.
+	(udivmodqi4): Ditto.
+	(absneg splitters): Ditto.
+	(*jcc_bt<mode>_1): Ditto.
+
 2016-04-19  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/70724
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3d044e8..a3ffee9 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14100,7 +14100,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out)
       else if (GET_CODE (addr) == AND
 	       && const_32bit_mask (XEXP (addr, 1), DImode))
 	{
-	  addr = simplify_gen_subreg (SImode, XEXP (addr, 0), DImode, 0);
+	  addr = lowpart_subreg (SImode, XEXP (addr, 0), DImode);
 	  if (addr == NULL_RTX)
 	    return 0;
 
@@ -16211,8 +16211,7 @@ ix86_delegitimize_address (rtx x)
 	  x = XVECEXP (XEXP (x, 0), 0, 0);
 	  if (GET_MODE (orig_x) != GET_MODE (x) && MEM_P (orig_x))
 	    {
-	      x = simplify_gen_subreg (GET_MODE (orig_x), x,
-				       GET_MODE (x), 0);
+	      x = lowpart_subreg (GET_MODE (orig_x), x, GET_MODE (x));
 	      if (x == NULL_RTX)
 		return orig_x;
 	    }
@@ -16303,7 +16302,7 @@ ix86_delegitimize_address (rtx x)
     }
   if (GET_MODE (orig_x) != Pmode && MEM_P (orig_x))
     {
-      result = simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
+      result = lowpart_subreg (GET_MODE (orig_x), result, Pmode);
       if (result == NULL_RTX)
 	return orig_x;
     }
@@ -19580,9 +19579,9 @@ ix86_split_idivmod (machine_mode mode, rtx operands[],
   emit_label (qimode_label);
   /* Don't use operands[0] for result of 8bit divide since not all
      registers support QImode ZERO_EXTRACT.  */
-  tmp0 = simplify_gen_subreg (HImode, scratch, mode, 0);
-  tmp1 = simplify_gen_subreg (HImode, operands[2], mode, 0);
-  tmp2 = simplify_gen_subreg (QImode, operands[3], mode, 0);
+  tmp0 = lowpart_subreg (HImode, scratch, mode);
+  tmp1 = lowpart_subreg (HImode, operands[2], mode);
+  tmp2 = lowpart_subreg (QImode, operands[3], mode);
   emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, tmp2));
 
   if (signed_p)
@@ -21016,7 +21015,7 @@ ix86_split_copysign_const (rtx operands[])
   mode = GET_MODE (dest);
   vmode = GET_MODE (mask);
 
-  dest = simplify_gen_subreg (vmode, dest, mode, 0);
+  dest = lowpart_subreg (vmode, dest, mode);
   x = gen_rtx_AND (vmode, dest, mask);
   emit_insn (gen_rtx_SET (dest, x));
 
@@ -21062,7 +21061,7 @@ ix86_split_copysign_var (rtx operands[])
       emit_insn (gen_rtx_SET (scratch, x));
 
       dest = mask;
-      op0 = simplify_gen_subreg (vmode, op0, mode, 0);
+      op0 = lowpart_subreg (vmode, op0, mode);
       x = gen_rtx_NOT (vmode, dest);
       x = gen_rtx_AND (vmode, x, op0);
       emit_insn (gen_rtx_SET (dest, x));
@@ -21076,21 +21075,21 @@ ix86_split_copysign_var (rtx operands[])
       else						/* alternative 2,4 */
 	{
           gcc_assert (REGNO (mask) == REGNO (scratch));
-          op1 = simplify_gen_subreg (vmode, op1, mode, 0);
+          op1 = lowpart_subreg (vmode, op1, mode);
 	  x = gen_rtx_AND (vmode, scratch, op1);
 	}
       emit_insn (gen_rtx_SET (scratch, x));
 
       if (REGNO (op0) == REGNO (dest))			/* alternative 1,2 */
 	{
-	  dest = simplify_gen_subreg (vmode, op0, mode, 0);
+	  dest = lowpart_subreg (vmode, op0, mode);
 	  x = gen_rtx_AND (vmode, dest, nmask);
 	}
       else						/* alternative 3,4 */
 	{
           gcc_assert (REGNO (nmask) == REGNO (dest));
 	  dest = nmask;
-	  op0 = simplify_gen_subreg (vmode, op0, mode, 0);
+	  op0 = lowpart_subreg (vmode, op0, mode);
 	  x = gen_rtx_AND (vmode, dest, op0);
 	}
       emit_insn (gen_rtx_SET (dest, x));
@@ -39115,7 +39114,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
   else
     {
       real_target = gen_reg_rtx (tmode);
-      target = simplify_gen_subreg (rmode, real_target, tmode, 0);
+      target = lowpart_subreg (rmode, real_target, tmode);
     }
 
   for (i = 0; i < nargs; i++)
@@ -39132,7 +39131,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
 	     count.  If count doesn't match, we put it in register.  */
 	  if (!match)
 	    {
-	      op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
+	      op = lowpart_subreg (SImode, op, GET_MODE (op));
 	      if (!insn_p->operand[i + 1].predicate (op, mode))
 		op = copy_to_reg (op);
 	    }
@@ -39288,7 +39287,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
 	  else
 	    {
 	      op = copy_to_reg (op);
-	      op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
+	      op = lowpart_subreg (mode, op, GET_MODE (op));
 	    }
 	}
 
@@ -39662,7 +39661,7 @@ ix86_expand_round_builtin (const struct builtin_description *d,
 	  else
 	    {
 	      op = copy_to_reg (op);
-	      op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
+	      op = lowpart_subreg (mode, op, GET_MODE (op));
 	    }
 	}
 
@@ -40060,7 +40059,7 @@ ix86_expand_special_args_builtin (const struct builtin_description *d,
 	      else
 	        {
 	          op = copy_to_reg (op);
-	          op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
+	          op = lowpart_subreg (mode, op, GET_MODE (op));
 	        }
 	    }
 	}
@@ -41276,9 +41275,9 @@ rdseed_step:
       op1 = expand_normal (arg1);
 
       op0 = copy_to_reg (op0);
-      op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0);
+      op0 = lowpart_subreg (mode0, op0, GET_MODE (op0));
       op1 = copy_to_reg (op1);
-      op1 = simplify_gen_subreg (mode0, op1, GET_MODE (op1), 0);
+      op1 = lowpart_subreg (mode0, op1, GET_MODE (op1));
 
       target = gen_reg_rtx (QImode);
       emit_insn (gen_rtx_SET (target, const0_rtx));
@@ -41669,7 +41668,7 @@ rdseed_step:
       else
 	{
 	  op3 = copy_to_reg (op3);
-	  op3 = simplify_gen_subreg (mode3, op3, GET_MODE (op3), 0);
+	  op3 = lowpart_subreg (mode3, op3, GET_MODE (op3));
 	}
       if (!insn_data[icode].operand[5].predicate (op4, mode4))
 	{
@@ -41844,7 +41843,7 @@ rdseed_step:
       else
 	{
 	  op1 = copy_to_reg (op1);
-	  op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
+	  op1 = lowpart_subreg (mode1, op1, GET_MODE (op1));
 	}
 
       if (!insn_data[icode].operand[2].predicate (op2, mode2))
@@ -41892,7 +41891,7 @@ rdseed_step:
       else
 	{
 	  op0 = copy_to_reg (op0);
-	  op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0);
+	  op0 = lowpart_subreg (mode0, op0, GET_MODE (op0));
 	}
 
       if (!insn_data[icode].operand[1].predicate (op1, mode1))
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index cf29e5d..6596a1d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4221,8 +4221,8 @@
 	     (match_dup 3)
 	     (parallel [(const_int 0) (const_int 1)]))))]
 {
-  operands[2] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
-  operands[3] = simplify_gen_subreg (V4SFmode, operands[0], DFmode, 0);
+  operands[2] = lowpart_subreg (V2DFmode, operands[0], DFmode);
+  operands[3] = lowpart_subreg (V4SFmode, operands[0], DFmode);
   /* Use movss for loading from memory, unpcklps reg, reg for registers.
      Try to avoid move when unpacking can be done in source.  */
   if (REG_P (operands[1]))
@@ -4239,7 +4239,7 @@
 	  emit_move_insn (tmp, operands[1]);
 	}
       else
-	operands[3] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
+	operands[3] = lowpart_subreg (V4SFmode, operands[1], SFmode);
       /* FIXME: vec_interleave_lowv4sf for AVX512VL should allow
 	 =v, v, then vbroadcastss will be only needed for AVX512F without
 	 AVX512VL.  */
@@ -4248,7 +4248,7 @@
 					       operands[3]));
       else
 	{
-	  rtx tmp = simplify_gen_subreg (V16SFmode, operands[3], V4SFmode, 0);
+	  rtx tmp = lowpart_subreg (V16SFmode, operands[3], V4SFmode);
 	  emit_insn (gen_avx512f_vec_dupv16sf_1 (tmp, tmp));
 	}
     }
@@ -4382,9 +4382,9 @@
 	     (match_dup 4))
 	   (match_dup 3)))]
 {
-  operands[2] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
+  operands[2] = lowpart_subreg (V4SFmode, operands[0], SFmode);
   operands[3] = CONST0_RTX (V2SFmode);
-  operands[4] = simplify_gen_subreg (V2DFmode, operands[0], SFmode, 0);
+  operands[4] = lowpart_subreg (V2DFmode, operands[0], SFmode);
   /* Use movsd for loading from memory, unpcklpd for registers.
      Try to avoid move when unpacking can be done in source, or SSE3
      movddup is available.  */
@@ -4395,12 +4395,12 @@
 	  && (ORIGINAL_REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
 	      || PSEUDO_REGNO_BYTES (ORIGINAL_REGNO (operands[1])) > 8))
 	{
-	  rtx tmp = simplify_gen_subreg (DFmode, operands[0], SFmode, 0);
+	  rtx tmp = lowpart_subreg (DFmode, operands[0], SFmode);
 	  emit_move_insn (tmp, operands[1]);
 	  operands[1] = tmp;
 	}
       else if (!TARGET_SSE3)
-	operands[4] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
+	operands[4] = lowpart_subreg (V2DFmode, operands[1], DFmode);
       emit_insn (gen_vec_dupv2df (operands[4], operands[1]));
     }
   else
@@ -5141,9 +5141,8 @@
        || TARGET_AVX512VL)"
   [(const_int 0)]
 {
-  operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
-				     <MODE>mode, 0);
-  operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0);
+  operands[3] = lowpart_subreg (<ssevecmode>mode, operands[0], <MODE>mode);
+  operands[4] = lowpart_subreg (V4SImode, operands[0], <MODE>mode);
 
   emit_insn (gen_sse2_loadld (operands[4],
 			      CONST0_RTX (V4SImode), operands[1]));
@@ -5169,7 +5168,7 @@
 {
   const machine_mode vmode = <MODEF:ssevecmode>mode;
   const machine_mode mode = <MODEF:MODE>mode;
-  rtx t, op0 = simplify_gen_subreg (vmode, operands[0], mode, 0);
+  rtx t, op0 = lowpart_subreg (vmode, operands[0], mode);
 
   emit_move_insn (op0, CONST0_RTX (vmode));
 
@@ -5202,10 +5201,8 @@
 	  (match_dup 0)
 	  (const_int 1)))]
 {
-  operands[0] = simplify_gen_subreg (V4SFmode, operands[0],
-				     SFmode, 0);
-  operands[1] = simplify_gen_subreg (V2DFmode, operands[1],
-				     DFmode, 0);
+  operands[0] = lowpart_subreg (V4SFmode, operands[0], SFmode);
+  operands[1] = lowpart_subreg (V2DFmode, operands[1], DFmode);
   emit_move_insn (operands[0], CONST0_RTX (V4SFmode));
 })
 
@@ -5232,10 +5229,8 @@
           (match_dup 0)
           (const_int 1)))]
 {
-  operands[0] = simplify_gen_subreg (V2DFmode, operands[0],
-				     DFmode, 0);
-  operands[1] = simplify_gen_subreg (V4SFmode, operands[1],
-				     SFmode, 0);
+  operands[0] = lowpart_subreg (V2DFmode, operands[0], DFmode);
+  operands[1] = lowpart_subreg (V4SFmode, operands[1], SFmode);
   emit_move_insn (operands[0], CONST0_RTX (V2DFmode));
 })
 
@@ -7703,14 +7698,13 @@
   tmp0 = gen_reg_rtx (HImode);
   tmp1 = gen_reg_rtx (HImode);
 
-  /* Extend operands[1] to HImode.  Generate 8bit divide.  Result is
-     in AX.  */
+  /* Extend operands[1] to HImode.  Generate 8bit divide.  Result is in AX.  */
   emit_insn (gen_zero_extendqihi2 (tmp1, operands[1]));
   emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, operands[2]));
 
   /* Extract remainder from AH.  */
   tmp1 = gen_rtx_ZERO_EXTRACT (SImode, tmp0, GEN_INT (8), GEN_INT (8));
-  tmp1 = simplify_gen_subreg (QImode, tmp1, SImode, 0);
+  tmp1 = lowpart_subreg (QImode, tmp1, SImode);
   rtx_insn *insn = emit_move_insn (operands[3], tmp1);
 
   mod = gen_rtx_UMOD (QImode, operands[1], operands[2]);
@@ -9320,8 +9314,8 @@
   machine_mode vmode = GET_MODE (operands[2]);
   rtx tmp;
 
-  operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
-  operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
+  operands[0] = lowpart_subreg (vmode, operands[0], mode);
+  operands[1] = lowpart_subreg (vmode, operands[1], mode);
   if (operands_match_p (operands[0], operands[2]))
     std::swap (operands[1], operands[2]);
   if (GET_CODE (operands[3]) == ABS)
@@ -11240,7 +11234,7 @@
 		      (label_ref (match_dup 3))
 		      (pc)))]
 {
-  operands[2] = simplify_gen_subreg (SImode, operands[2], QImode, 0);
+  operands[2] = lowpart_subreg (SImode, operands[2], QImode);
   operands[0] = shallow_copy_rtx (operands[0]);
   PUT_CODE (operands[0], reverse_condition (GET_CODE (operands[0])));
 })