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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2023-04-11 11:04:56 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-04-17 11:13:41 -0700 |
| commit | 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368 (patch) | |
| tree | b57a9b941f8b1318429f7f4c0f5b9162b2f3ec32 /gcc | |
| parent | a782346757c54a5a3cfb9f416a7ebe3554a617d7 (diff) | |
| download | gcc-8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368.zip gcc-8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368.tar.gz gcc-8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368.tar.bz2 | |
RISC-V: Clean up the pr106602.c testcase
The test case that was added is rv64i-specific, as there's better ways
to generate this code on rv32i (where the long/int cast is a NOP) and on
rv64i_zba (where we have word shifts). This renames the original test
case and adds two more for those targets.
gcc/testsuite/ChangeLog:
PR target/106602
* gcc.target/riscv/pr106602.c: Moved to...
* gcc.target/riscv/pr106602-rv64i.c: ...here.
* gcc.target/riscv/pr106602-rv32i.c: New test.
* gcc.target/riscv/pr106602-rv64i_zba.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c | 14 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c (renamed from gcc/testsuite/gcc.target/riscv/pr106602.c) | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c | 15 |
3 files changed, 30 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c new file mode 100644 index 0000000..05b54db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-O2 -march=rv32i -mabi=ilp32" } */ + +unsigned long +foo2 (unsigned long a) +{ + return (unsigned long)(unsigned int) a << 6; +} + +/* { dg-final { scan-assembler-times "slli\t" 1 } } */ +/* { dg-final { scan-assembler-not "srli\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ +/* { dg-final { scan-assembler-not "and\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c index 825b1a1..ef0719f 100644 --- a/gcc/testsuite/gcc.target/riscv/pr106602.c +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { riscv64*-*-* } } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -march=rv64i -mabi=lp64" } */ unsigned long foo2 (unsigned long a) diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c new file mode 100644 index 0000000..23b9f1e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-O2 -march=rv64i_zba -mabi=lp64" } */ + +unsigned long +foo2 (unsigned long a) +{ + return (unsigned long)(unsigned int) a << 6; +} + +/* { dg-final { scan-assembler-times "slli.uw\t" 1 } } */ +/* { dg-final { scan-assembler-not "slli\t" } } */ +/* { dg-final { scan-assembler-not "srli\t" } } */ +/* { dg-final { scan-assembler-not "\tli\t" } } */ +/* { dg-final { scan-assembler-not "addi\t" } } */ +/* { dg-final { scan-assembler-not "and\t" } } */ |