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| author | Yixuan Chen <chenyixuan@iscas.ac.cn> | 2024-09-24 09:15:00 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-24 09:16:49 -0600 |
| commit | 79a3d3da8c8a5ad56547b7f7991577271ee5d1b2 (patch) | |
| tree | 725b7090b83b49cb24608f87aec2c9007b475077 /gcc | |
| parent | 96246bff0bcd9e5cdec9e6cf811ee3db4997f6d4 (diff) | |
| download | gcc-79a3d3da8c8a5ad56547b7f7991577271ee5d1b2.zip gcc-79a3d3da8c8a5ad56547b7f7991577271ee5d1b2.tar.gz gcc-79a3d3da8c8a5ad56547b7f7991577271ee5d1b2.tar.bz2 | |
[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register
gcc/ChangeLog:
* config/riscv/riscv.h: Fix FIXED_REGISTERS comment missing return
address register.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index ead9786..3aecb43 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -316,7 +316,7 @@ ASM_MISA_SPEC #define FIRST_PSEUDO_REGISTER 128 -/* x0, sp, gp, and tp are fixed. */ +/* x0, ra, sp, gp, and tp are fixed. */ #define FIXED_REGISTERS \ { /* General registers. */ \ |