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author | xuli <xuli1@eswincomputing.com> | 2024-07-11 04:29:11 +0000 |
---|---|---|
committer | xuli <xuli1@eswincomputing.com> | 2024-07-12 08:05:24 +0000 |
commit | 63d7d5998e3768f6e3703c29e8774e8b54af108c (patch) | |
tree | 0b0d278900c74987ad4dd4b34d4188e90ba658dd /gcc | |
parent | 3ea47ea1fcab95fd1b80acc724fdbb27fc436985 (diff) | |
download | gcc-63d7d5998e3768f6e3703c29e8774e8b54af108c.zip gcc-63d7d5998e3768f6e3703c29e8774e8b54af108c.tar.gz gcc-63d7d5998e3768f6e3703c29e8774e8b54af108c.tar.bz2 |
RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]
The reason is that in the following code, icode = movmisalignv8si has
already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
allowed by targetm.slow_unaligned_access,which is contradictory.
(((icode = optab_handler (movmisalign_optab, mode))
!= CODE_FOR_nothing)
|| targetm.slow_unaligned_access (mode, align))
misaligned vector access should be enabled by -mno-vector-strict-align option.
PR target/115862
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector misalign.
Signed-off-by: Li Xu <xuli1@eswincomputing.com>
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/riscv.cc | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 |
2 files changed, 55 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 61fa74e..16b210f3 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -10269,9 +10269,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn) /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */ static bool -riscv_slow_unaligned_access (machine_mode, unsigned int) +riscv_slow_unaligned_access (machine_mode mode, unsigned int) { - return riscv_slow_unaligned_access_p; + return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED + : riscv_slow_unaligned_access_p; } static bool diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c new file mode 100644 index 0000000..3cbc3c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */ + +struct mallinfo2 +{ + int arena; + int ordblks; + int smblks; + int hblks; + int hblkhd; + int usmblks; + int fsmblks; + int uordblks; + int fordblks; + int keepcost; +}; + +struct mallinfo +{ + int arena; + int ordblks; + int smblks; + int hblks; + int hblkhd; + int usmblks; + int fsmblks; + int uordblks; + int fordblks; + int keepcost; +}; + +struct mallinfo +__libc_mallinfo (void) +{ + struct mallinfo m; + struct mallinfo2 m2; + + m.arena = m2.arena; + m.ordblks = m2.ordblks; + m.smblks = m2.smblks; + m.hblks = m2.hblks; + m.hblkhd = m2.hblkhd; + m.usmblks = m2.usmblks; + m.fsmblks = m2.fsmblks; + m.uordblks = m2.uordblks; + m.fordblks = m2.fordblks; + m.keepcost = m2.keepcost; + + return m; +} + +/* { dg-final { scan-assembler {vle32\.v} } } */ |