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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-10-10 07:23:26 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-10-10 11:22:56 +0800 |
| commit | 4ecb9b03d9a058925d5a5bc43bdc3a505a587b0c (patch) | |
| tree | 126713353871778c0be9cb85e4b395e1a9f50686 /gcc | |
| parent | fb124f2a23e92b08556984a50a4b2f367ed04d90 (diff) | |
| download | gcc-4ecb9b03d9a058925d5a5bc43bdc3a505a587b0c.zip gcc-4ecb9b03d9a058925d5a5bc43bdc3a505a587b0c.tar.gz gcc-4ecb9b03d9a058925d5a5bc43bdc3a505a587b0c.tar.bz2 | |
RISC-V: Add available vector size for RVV
For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
from M1 to M8.
For example, when TARGET_MIN_VLEN = 128 bits, we enable
128/256/512/1024 bits VLS modes.
This patch fixes following FAIL:
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "optimized: basic block" 2
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 2
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add 256/512/1024
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index af52c38..dc366d3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8881,7 +8881,7 @@ proc available_vector_sizes { } { lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 } elseif { [istarget riscv*-*-*] } { if { [check_effective_target_riscv_v] } { - lappend result 0 32 64 128 + lappend result 0 32 64 128 256 512 1024 } lappend result 128 } else { |