Daily bump.

7 files changed, 470 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a642c78..23ee454 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,226 @@
+2024-11-09  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	PR target/117408
+	* config/arm/arm-mve-builtins.cc(handle_arm_mve_h): Detect if MVE
+	types is missing and if so, return error.
+
+2024-11-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* trans-mem.cc (expand_assign_tm): Don't take address
+	of empty CONSTRUCTOR, instead use BUILT_IN_TM_MEMSET
+	to clear lhs in that case.  Formatting fixes.
+
+2024-11-09  Andi Kleen  <ak@gcc.gnu.org>
+
+	* config/i386/gcc-auto-profile: Regenerate.
+
+2024-11-08  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR target/117238
+	* config/pa/pa64-regs.h (PA_HARD_REGNO_MODE_OK): Don't allow
+	mode size 32.
+
+2024-11-08  John David Anglin  <danglin@gcc.gnu.org>
+
+	* config/pa/predicates.md (base14_operand): Use '&' operator
+	instead of '%' to check displacement alignment.
+
+2024-11-08  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR target/117238
+	* config/pa/pa32-regs.h (PA_HARD_REGNO_MODE_OK): Don't allow
+	mode size 32.  Limit mode size 16 in general registers to
+	complex modes.
+
+2024-11-08  John David Anglin  <danglin@gcc.gnu.org>
+
+	PR target/117443
+	* config/pa/pa.cc (pa_legitimate_address_p): Allow any
+	14-bit displacement when reload is in progress and strict
+	is false.
+
+2024-11-08  Andre Simoes Dias Vieira  <andre.simoesdiasvieira@arm.com>
+
+	PR target/116444
+	* config/arm/arm.cc (arm_noce_conversion_profitable_p): Call
+	default_noce_conversion_profitable_p when not dealing with the
+	armv8.1-m.main special case.
+	(arm_is_vsel_fp_insn): New function.
+
+2024-11-08  Victor Do Nascimento  <victor.donascimento@arm.com>
+
+	* config/aarch64/aarch64-cores.def (cortex-a520ae,
+	cortex-a720ae, cortex-r82ae): Define new entries.
+	* config/aarch64/aarch64-tune.md: Regenerate.
+	* doc/invoke.texi: Document A520AE, A720AE and R82AE CPUs.
+
+2024-11-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sve2.md (@aarch64_sve_psel<BHSD_BITS>)
+	(*aarch64_sve_psel<BHSD_BITS>_plus): Require TARGET_STREAMING
+	rather than TARGET_STREAMING_SME2.
+
+2024-11-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sve2.md (@aarch64_sve_fclamp<mode>)
+	(*aarch64_sve_fclamp<mode>_x): Require TARGET_STREAMING_SME2
+	rather than TARGET_STREAMING_SME.
+
+2024-11-07  David Faust  <david.faust@oracle.com>
+
+	PR target/117447
+	* config/bpf/btfext-out.cc (btf_ext_output): Bail if TU CTFC is null.
+
+2024-11-07  David Faust  <david.faust@oracle.com>
+
+	* btfout.cc (btf_finalize): Check that hash maps are non-null before
+	emptying them.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/85605
+	* tree-ssa-ifcombine.cc (can_combine_bbs_with_short_circuit): New function.
+	(ifcombine_ifandif): Use can_combine_bbs_with_short_circuit
+	instead of checking if iterator is one before the last statement.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* tree-ssa-sccvn.cc (process_bb): Lookup
+	`val != 0` if got back a ssa name when looking the comparison.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* tree-ssa-sccvn.cc (insert_predicates_for_cond): Handle `(A CMP B) !=/== 0`.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* tree-ssa-sccvn.cc (insert_predicates_for_cond): Canonicalize the comparison.
+	Don't insert anything if lhs is not a SSA_NAME. Handle `(a | b) !=/== 0`.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	* tree-ssa-sccvn.cc (insert_predicates_for_cond): New function, factored out from ...
+	(process_bb): Here.
+
+2024-11-07  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-data-refs.cc (vect_check_gather_scatter): Refuse
+	to analyze DR_REF if from an epilogue that's not first.
+	* tree-vect-loop.cc (update_epilogue_loop_vinfo): Add comment
+	how the substitution in DR_REF is broken.
+
+2024-11-07  Richard Biener  <rguenther@suse.de>
+
+	* tree-vectorizer.h (_loop_vec_info::main_loop_info): New.
+	(LOOP_VINFO_MAIN_LOOP_INFO): Likewise.
+	(_loop_vec_info::epilogue_vinfo): Change from epilogue_vinfos
+	from array to single element.
+	* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
+	main_loop_info and epilogue_vinfo.  Remove epilogue_vinfos
+	allocation.
+	(_loop_vec_info::~_loop_vec_info): Do not release epilogue_vinfos.
+	(vect_create_loop_vinfo): Rename parameter, set
+	LOOP_VINFO_MAIN_LOOP_INFO.
+	(vect_analyze_loop_1): Rename parameter.
+	(vect_analyze_loop_costing): Properly distinguish between
+	the main vector loop and the preceeding epilogue.
+	(vect_analyze_loop): Change for epilogue_vinfos no longer
+	being a vector.
+	* tree-vect-loop-manip.cc (vect_do_peeling): Simplify and
+	thereby handle a vector epilogue of a vector epilogue.
+
+2024-11-07  Richard Biener  <rguenther@suse.de>
+
+	* tree-vectorizer.h (_loop_vec_info::drs_advanced_by): New.
+	(LOOP_VINFO_DRS_ADVANCED_BY): Likewise.
+	* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
+	drs_advanced_by.
+	(update_epilogue_loop_vinfo): Remember the DR advancement made.
+	(vect_transform_loop): Accumulate past advancements.
+
+2024-11-07  Richard Biener  <rguenther@suse.de>
+
+	* tree-vect-loop.cc (vect_analyze_loop_2): Move
+	vect_analyze_loop_costing after check whether we can do
+	peeling.  Add check on LOOP_VINFO_PEELING_FOR_GAPS for
+	epilogues.
+
+2024-11-07  Pan Li  <pan2.li@intel.com>
+	    Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+	* doc/md.texi: Add doc for mask_len_stried_load{store}.
+
+2024-11-07  Richard Biener  <rguenther@suse.de>
+
+	PR rtl-optimization/117467
+	* timevar.def (TV_EXT_DCE): New.
+	* ext-dce.cc (pass_data_ext_dce): Use TV_EXT_DCE.
+
+2024-11-07  Hongyu Wang  <hongyu.wang@intel.com>
+
+	* config/i386/i386.md (cstorebf4): Use vcomsbf16 under
+	TARGET_AVX10_2_256 and -fno-trapping-math.
+	(cbranchbf4): Adjust formatting.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc
+	(ifcombine_rewrite_to_defined_overflow): New.
+	(ifcombine_replace_cond): Reject conds that would require
+	moving too many stmts.  Reset flow sensitive info and avoid
+	undefined behavior in moved stmts.  Reset flow sensitive info
+	in all inner blocks when the outer condition changes, and
+	avoid undefined behavior whenever the outer condition becomes
+	laxer, adapted and moved from...
+	(pass_tree_ifcombine::execute): ... here.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc (recognize_if_then_else): Support
+	relaxed then/else testing; require nondegenerate condition
+	otherwise.
+	(tree_ssa_ifcombine_bb_1): Add outer_succ_bb parm, use it
+	instead of inner_cond_bb.  Adjust callers.
+	(tree_ssa_ifcombine_bb): Loop over dominating outer blocks
+	eligible for ifcombine.
+	(pass_tree_ifcombine::execute): Noted potential need for
+	changes to the post-combine logic.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc: Include bitmap.h.
+	(ifcombine_mark_ssa_name): New.
+	(struct ifcombine_mark_ssa_name_t): New.
+	(ifcombine_mark_ssa_name_walk): New.
+	(ifcombine_replace_cond): Prepare to handle noncontiguous and
+	split-condition ifcombine.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc (known_succ_p): New.
+	(update_profile_after_ifcombine): Handle noncontiguous blocks.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc (ifcombine_replace_cond): Factor out
+	of...
+	(ifcombine_ifandif): ... this.  Leave it for the above to
+	gimplify and invert the condition.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* tree-ssa-ifcombine.cc (ifcombine_ifandif): Drop redundant
+	result_inv parm.  Adjust all callers.
+
+2024-11-07  xuli  <xuli1@eswincomputing.com>
+
+	* match.pd: Add the form1 of signed imm .SAT_ADD matching.
+	* tree-ssa-math-opts.cc (match_saturation_add): Add fold
+	convert	for const_int to the type of operand 0.
+
 2024-11-06  Alexey Merzlyakov  <alexey.merzlyakov@samsung.com>
 
 	PR rtl-optimization/112398
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 6d8a676..7731736 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241107
+20241109
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 6a5053a..5b98fb6 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,11 @@
+2024-11-07  Paul Iannetta  <piannetta@kalrayinc.com>
+
+	* c-pragma.cc (struct pragma_pp_data): Use (struct internal_pragma_handler);
+	(c_register_pragma_1): Always register name and space for all pragmas.
+	(c_invoke_pragma_handler): Adapt.
+	(c_invoke_early_pragma_handler): Likewise.
+	(c_pp_invoke_early_pragma_handler): Likewise.
+
 2024-11-01  Jakub Jelinek  <jakub@redhat.com>
 
 	* c.opt (std=c++2b, std=c++23, std=gnu++2b, std=gnu++23): Adjust
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index c9d0c8c..ca460e4 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,36 @@
+2024-11-09  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/116284
+	PR c/117391
+	* c-tree.h (c_type_unspecified_p): New inline function.
+	* c-typeck.cc (c_build_array_type_unspecified): New function.
+	(comptypes_interal): Remove useless code.
+	(composite_type_internal): Update.
+	* c-decl.cc (grokdeclarator): Revise.
+
+2024-11-08  Marek Polacek  <polacek@redhat.com>
+
+	PR c/117019
+	* c-parser.cc (c_parser_declaration_or_fndef): Adjust declaration.
+	(c_parser_external_declaration): Adjust a call to
+	c_parser_declaration_or_fndef.
+	(c_parser_declaration_or_fndef): New bool parameter.  Return a tree
+	instead of void.  Adjust for N3356.  Adjust a call to
+	c_parser_declaration_or_fndef.
+	(c_parser_compound_statement_nostart): Adjust calls to
+	c_parser_declaration_or_fndef.
+	(c_parser_selection_header): New.
+	(c_parser_paren_selection_header): New.
+	(c_parser_if_statement): Call c_parser_paren_selection_header
+	instead of c_parser_paren_condition.
+	(c_parser_switch_statement): Call c_parser_selection_header instead of
+	c_parser_expression.
+	(c_parser_for_statement): Adjust calls to c_parser_declaration_or_fndef.
+	(c_parser_objc_methodprotolist): Likewise.
+	(c_parser_oacc_routine): Likewise.
+	(c_parser_omp_loop_nest): Likewise.
+	(c_parser_omp_declare_simd): Likewise.
+
 2024-11-05  Andrew Pinski  <quic_apinski@quicinc.com>
 
 	PR c/117445
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index fdb726c..b0673ee 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2024-11-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/117317
+	* semantics.cc (emit_associated_thunks): Do nothing for
+	!DECL_INTERFACE_KNOWN && DECL_DEFER_OUTPUT fns.
+
 2024-11-05  Jason Merrill  <jason@redhat.com>
 
 	PR c++/116634
diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index c22f80f..af7fc09 100644
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,8 @@
+2024-11-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* Make-lang.in (m2_OBJS): Add $(BUILD-LIBS-BOOT),
+	$(BUILD-COMPILER-BOOT) and $(MC_LIBS).
+
 2024-10-25  Jakub Jelinek  <jakub@redhat.com>
 
 	* mc-boot/GFpuIO.cc: Remove trailing whitespace.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e98fc85..0ab603c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,197 @@
+2024-11-09  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	PR target/117408
+	* gcc.target/arm/mve/pr117408-1.c: New test.
+	* gcc.target/arm/mve/pr117408-2.c: Likewise.
+
+2024-11-09  Martin Uecker  <uecker@tugraz.at>
+
+	PR c/116284
+	PR c/117391
+	* gcc.dg/pr116284.c: New test.
+	* gcc.dg/pr117391.c: New test.
+
+2024-11-08  Marek Polacek  <polacek@redhat.com>
+
+	PR c/117019
+	* gcc.dg/c23-if-decls-1.c: New test.
+	* gcc.dg/c23-if-decls-2.c: New test.
+	* gcc.dg/c2y-if-decls-1.c: New test.
+	* gcc.dg/c2y-if-decls-2.c: New test.
+	* gcc.dg/c2y-if-decls-3.c: New test.
+	* gcc.dg/c2y-if-decls-4.c: New test.
+	* gcc.dg/c2y-if-decls-5.c: New test.
+	* gcc.dg/c2y-if-decls-6.c: New test.
+	* gcc.dg/c2y-if-decls-7.c: New test.
+	* gcc.dg/c2y-if-decls-8.c: New test.
+	* gcc.dg/c2y-if-decls-9.c: New test.
+	* gcc.dg/c2y-if-decls-10.c: New test.
+	* gcc.dg/c2y-if-decls-11.c: New test.
+	* gcc.dg/gnu2y-if-decls-1.c: New test.
+	* gcc.dg/gnu99-if-decls-1.c: New test.
+	* gcc.dg/gnu99-if-decls-2.c: New test.
+
+2024-11-08  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/bb-slp-77.c: Add x86_64-*-* and i?86-*-* to
+	the list of expected failing targets.
+
+2024-11-08  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/117317
+	* g++.dg/cpp2a/pr117317-1.C: New test.
+	* g++.dg/cpp2a/pr117317-2.C: New test.
+
+2024-11-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	* gcc.target/arm/epilog-1.c: Use check-function-bodies.
+
+2024-11-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+	    Richard Earnshaw  <rearnsha@arm.com>
+
+	* gcc.target/arm/pr68620.c: Use effective-target
+	arm_libc_fp_abi.
+	* lib/target-supports.exp: Define effective-target
+	arm_libc_fp_abi.
+
+2024-11-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	* gcc.target/arm/pr40457-2.c: Add vst1.32 as an allowed
+	instruction.
+
+2024-11-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	* g++.dg/vect/pr84556.cc: Change from "dg-do run" with selector
+	to instead use dg-require-effective-target with the same
+	selector.
+
+2024-11-08  Richard Biener  <rguenther@suse.de>
+
+	* gcc.dg/vect/vect-early-break_21.c: Remove disabling of
+	x86_64 and i?86.
+
+2024-11-08  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+
+	* g++.target/arm/mve/general-c++/nomve_fp_1.c: Use
+	effective-target arm_fp.
+
+2024-11-08  xuli  <xuli1@eswincomputing.com>
+
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub.
+	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: add unsigned imm vec sat_sub form1.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: New test.
+	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: New test.
+
+2024-11-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c: Replace bfmla*
+	with bfmls*
+
+2024-11-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c: ...here.
+	* gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c: Move to...
+	* gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c: ...here.
+
+2024-11-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/sme/clamp_3.c: Force sme2
+	* gcc.target/aarch64/sme/clamp_4.c: Likewise.
+	* gcc.target/aarch64/sme/clamp_5.c: New test.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/85605
+	* g++.dg/tree-ssa/ifcombine-ccmp-1.C: New test.
+	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-7.c: New test.
+	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-8.c: New test.
+	* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-9.c: New test.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* gcc.dg/tree-ssa/fre-predicated-4.c: New test.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* gcc.dg/tree-ssa/fre-predicated-3.c: New test.
+
+2024-11-07  Andrew Pinski  <quic_apinski@quicinc.com>
+
+	PR tree-optimization/117414
+	* gcc.dg/tree-ssa/fre-predicated-1.c: New test.
+	* gcc.dg/tree-ssa/fre-predicated-2.c: New test.
+
+2024-11-07  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/116725
+	* gcc.target/i386/pr116725.c: Add dg-require-effective-target
+	avx512{dq,fp16,vl}.
+
+2024-11-07  Andrew Stubbs  <ams@baylibre.com>
+
+	* gcc.dg/gomp/max_vf-1.c: Add -mno-avx.
+
+2024-11-07  Hongyu Wang  <hongyu.wang@intel.com>
+
+	* gcc.target/i386/avx10_2-comibf-3.c: New test.
+	* gcc.target/i386/avx10_2-comibf-4.c: Likewise.
+
+2024-11-07  Hu, Lin1  <lin1.hu@intel.com>
+
+	* gcc.target/i386/pr117304-1.c: Modify regexp.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* gcc.target/i386/no-callee-saved-13.c: Disable PIE on ia32.
+	* gcc.target/i386/no-callee-saved-14.c: Likewise.
+	* gcc.target/i386/no-callee-saved-15.c: Likewise.
+	* gcc.target/i386/no-callee-saved-17.c: Likewise.
+	* gcc.target/i386/pr100865-1.c: Likewise.
+	* gcc.target/i386/pr100865-7a.c: Likewise.
+	* gcc.target/i386/pr100865-7c.c: Likewise.
+	* gcc.target/i386/sse2-stv-1.c: Likewise.
+
+2024-11-07  Alexandre Oliva  <oliva@adacore.com>
+
+	* gcc.target/i386/pr70321.c: Cope with non-bx get_pc_thunk.
+
+2024-11-07  xuli  <xuli1@eswincomputing.com>
+
+	* gcc.target/riscv/sat_arith.h: Support signed
+	imm SAT_ADD form1.
+	* gcc.target/riscv/sat_s_add_imm-1-1.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-1.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-2-1.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-2.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-3-1.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-3.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-4.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-run-1.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-run-2.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-run-3.c: New test.
+	* gcc.target/riscv/sat_s_add_imm-run-4.c: New test.
+
 2024-11-06  H.J. Lu  <hjl.tools@gmail.com>
 
 	* gcc.target/i386/avx10_2-comibf-2.c: Require avx10_2 target.