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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-23 14:40:17 +0100 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2023-04-23 14:40:17 +0100 |
| commit | 3b13c59c835f92b353ef318398e39907cdeec4fa (patch) | |
| tree | 32ea46cf8026aaa367f8f00e0da24f7c1e9cdc65 /gcc | |
| parent | 8ffff5e9de2fa8e2845c8045941afbb1e8638aed (diff) | |
| download | gcc-3b13c59c835f92b353ef318398e39907cdeec4fa.zip gcc-3b13c59c835f92b353ef318398e39907cdeec4fa.tar.gz gcc-3b13c59c835f92b353ef318398e39907cdeec4fa.tar.bz2 | |
aarch64: Add vect_concat with zeroes annotation to addp pattern
Similar to others, the addp pattern can be safely annotated with <vczle><vczbe> to create
the implicit vec_concat-with-zero variants.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_addp<mode>): Rename to...
(aarch64_addp<mode><vczle><vczbe>): ... This.
gcc/testsuite/ChangeLog:
PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add testing for vpadd intrinsics.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c | 17 |
2 files changed, 12 insertions, 7 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index adcad56..4a1ec71 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -6767,7 +6767,7 @@ ;; addp -(define_insn "aarch64_addp<mode>" +(define_insn "aarch64_addp<mode><vczle><vczbe>" [(set (match_operand:VDQ_I 0 "register_operand" "=w") (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w") diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c index 3ddd5a3..3fe0e53 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_1.c @@ -37,13 +37,18 @@ OPFOUR (T, IS, OS, S, OP2, OP3, OP4, OP5) FUNC (T, IS, OS, OP1, S) \ OPFIVE (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6) -OPSIX (int8, 8, 16, s8, add, sub, mul, and, orr, eor) -OPSIX (int16, 4, 8, s16, add, sub, mul, and, orr, eor) -OPSIX (int32, 2, 4, s32, add, sub, mul, and, orr, eor) +#define OPSEVEN(T,IS,OS,S,OP1,OP2,OP3,OP4,OP5,OP6,OP7) \ +FUNC (T, IS, OS, OP1, S) \ +OPSIX (T, IS, OS, S, OP2, OP3, OP4, OP5, OP6, OP7) + + +OPSEVEN (int8, 8, 16, s8, padd, add, sub, mul, and, orr, eor) +OPSEVEN (int16, 4, 8, s16, padd, add, sub, mul, and, orr, eor) +OPSEVEN (int32, 2, 4, s32, padd, add, sub, mul, and, orr, eor) -OPSIX (uint8, 8, 16, u8, add, sub, mul, and, orr, eor) -OPSIX (uint16, 4, 8, u16, add, sub, mul, and, orr, eor) -OPSIX (uint32, 2, 4, u32, add, sub, mul, and, orr, eor) +OPSEVEN (uint8, 8, 16, u8, padd, add, sub, mul, and, orr, eor) +OPSEVEN (uint16, 4, 8, u16, padd, add, sub, mul, and, orr, eor) +OPSEVEN (uint32, 2, 4, u32, padd, add, sub, mul, and, orr, eor) /* { dg-final { scan-assembler-not {\tfmov\t} } } */ /* { dg-final { scan-assembler-not {\tmov\t} } } */ |