PR target/116365: Add user-friendly arguments to --param aarch64-autovec-preference=N

The param aarch64-autovec-preference=N is a useful tool for testing
auto-vectorisation in GCC as it allows the user to force a particular
strategy. So far, N could be a numerical value between 0 and 4.
This patch replaces the numerical values by more user-friendly
names to distinguish the options.

The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
Ok for mainline?

Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>

gcc/
	PR target/116365
	* config/aarch64/aarch64-opts.h
	(enum aarch64_autovec_preference_enum):	New enum.
	* config/aarch64/aarch64.cc (aarch64_cmp_autovec_modes):
	Change numerical to enum values.
	(aarch64_autovectorize_vector_modes): Change numerical to enum
	values.
	(aarch64_vector_costs::record_potential_advsimd_unrolling):
	Change numerical to enum values.
	* config/aarch64/aarch64.opt: Change param type to enum.
	* doc/invoke.texi: Update documentation.

gcc/testsuite/
	PR target/116365
	* gcc.target/aarch64/autovec_param_asimd-only.c: New test.
	* gcc.target/aarch64/autovec_param_default.c: Likewise.
	* gcc.target/aarch64/autovec_param_prefer-asimd.c: Likewise.
	* gcc.target/aarch64/autovec_param_prefer-sve.c: Likewise.
	* gcc.target/aarch64/autovec_param_sve-only.c: Likewise.
	* gcc.target/aarch64/neoverse_v1_2.c: Update parameter value.
	* gcc.target/aarch64/neoverse_v1_3.c: Likewise.
	* gcc.target/aarch64/sve/cond_asrd_1.c: Likewise.
	* gcc.target/aarch64/sve/cond_cnot_4.c: Likewise.
	* gcc.target/aarch64/sve/cond_unary_5.c: Likewise.
	* gcc.target/aarch64/sve/cond_uxt_5.c: Likewise.
	* gcc.target/aarch64/sve/cond_xorsign_2.c: Likewise.
	* gcc.target/aarch64/sve/pr98268-1.c: Likewise.
	* gcc.target/aarch64/sve/pr98268-2.c: Likewise.

18 files changed, 80 insertions, 25 deletions

diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h
index 80ec1a0..9fb62e5 100644
--- a/gcc/config/aarch64/aarch64-opts.h
+++ b/gcc/config/aarch64/aarch64-opts.h
@@ -115,6 +115,23 @@ enum aarch64_key_type {
   AARCH64_KEY_B
 };
 
+/* An enum for setting the auto-vectorization preference:
+   - AARCH64_AUTOVEC_DEFAULT: Use default heuristics
+   - AARCH64_AUTOVEC_ASIMD_ONLY: Use only Advanced SIMD (Neon)
+   for auto-vectorisation
+   - AARCH64_AUTOVEC_SVE_ONLY: Use only SVE for auto-vectorisation
+   - AARCH64_AUTOVEC_PREFER_ASIMD: Use both Neon and SVE,
+   but prefer Neon when the costs are equal
+   - AARCH64_AUTOVEC_PREFER_SVE: Use both Neon and SVE,
+   but prefer SVE when the costs are equal.  */
+enum aarch64_autovec_preference_enum {
+  AARCH64_AUTOVEC_DEFAULT,
+  AARCH64_AUTOVEC_ASIMD_ONLY,
+  AARCH64_AUTOVEC_SVE_ONLY,
+  AARCH64_AUTOVEC_PREFER_ASIMD,
+  AARCH64_AUTOVEC_PREFER_SVE
+};
+
 /* An enum specifying how to handle load and store pairs using
    a fine-grained policy:
    - LDP_STP_POLICY_DEFAULT: Use the policy defined in the tuning structure.
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 4e312c4..69afcc6 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -16405,7 +16405,7 @@ record_potential_advsimd_unrolling (loop_vec_info loop_vinfo)
 
   /* Check whether it is possible in principle to use Advanced SIMD
      instead.  */
-  if (aarch64_autovec_preference == 2)
+  if (aarch64_autovec_preference == AARCH64_AUTOVEC_SVE_ONLY)
     return;
 
   /* We don't want to apply the heuristic to outer loops, since it's
@@ -22311,8 +22311,8 @@ static bool
 aarch64_cmp_autovec_modes (machine_mode sve_m, machine_mode asimd_m)
 {
   /* Take into account the aarch64-autovec-preference param if non-zero.  */
-  bool only_asimd_p = aarch64_autovec_preference == 1;
-  bool only_sve_p = aarch64_autovec_preference == 2;
+  bool only_asimd_p = aarch64_autovec_preference == AARCH64_AUTOVEC_ASIMD_ONLY;
+  bool only_sve_p = aarch64_autovec_preference == AARCH64_AUTOVEC_SVE_ONLY;
 
   if (only_asimd_p)
     return false;
@@ -22320,8 +22320,8 @@ aarch64_cmp_autovec_modes (machine_mode sve_m, machine_mode asimd_m)
     return true;
 
   /* The preference in case of a tie in costs.  */
-  bool prefer_asimd = aarch64_autovec_preference == 3;
-  bool prefer_sve = aarch64_autovec_preference == 4;
+  bool prefer_asimd = aarch64_autovec_preference == AARCH64_AUTOVEC_PREFER_ASIMD;
+  bool prefer_sve = aarch64_autovec_preference == AARCH64_AUTOVEC_PREFER_SVE;
 
   poly_int64 nunits_sve = GET_MODE_NUNITS (sve_m);
   poly_int64 nunits_asimd = GET_MODE_NUNITS (asimd_m);
@@ -22422,8 +22422,8 @@ aarch64_autovectorize_vector_modes (vector_modes *modes, bool)
        than an SVE main loop with N bytes then by default we'll try to
        use the SVE loop to vectorize the epilogue instead.  */
 
-  bool only_asimd_p = aarch64_autovec_preference == 1;
-  bool only_sve_p = aarch64_autovec_preference == 2;
+  bool only_asimd_p = aarch64_autovec_preference == AARCH64_AUTOVEC_ASIMD_ONLY;
+  bool only_sve_p = aarch64_autovec_preference == AARCH64_AUTOVEC_SVE_ONLY;
 
   unsigned int sve_i = (TARGET_SVE && !only_asimd_p) ? 0 : ARRAY_SIZE (sve_modes);
   unsigned int advsimd_i = 0;
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 6229bcb..c2c9965 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -352,7 +352,27 @@ Target Joined UInteger Var(aarch64_double_recp_precision) Init(2) IntegerRange(1
 The number of Newton iterations for calculating the reciprocal for double type.  The precision of division is proportional to this param when division approximation is enabled.  The default value is 2.
 
 -param=aarch64-autovec-preference=
-Target Joined UInteger Var(aarch64_autovec_preference) Init(0) IntegerRange(0, 4) Param
+Target Joined Var(aarch64_autovec_preference) Enum(aarch64_autovec_preference) Init(AARCH64_AUTOVEC_DEFAULT) Param
+--param=aarch64-autovec-preference=[default|asimd-only|sve-only|prefer-asimd|prefer-sve]
+Force an ISA selection strategy for auto-vectorization.
+
+Enum
+Name(aarch64_autovec_preference) Type(enum aarch64_autovec_preference_enum) UnknownError(unknown autovec preference %qs)
+
+EnumValue
+Enum(aarch64_autovec_preference) String(default) Value(AARCH64_AUTOVEC_DEFAULT)
+
+EnumValue
+Enum(aarch64_autovec_preference) String(asimd-only) Value(AARCH64_AUTOVEC_ASIMD_ONLY)
+
+EnumValue
+Enum(aarch64_autovec_preference) String(sve-only) Value(AARCH64_AUTOVEC_SVE_ONLY)
+
+EnumValue
+Enum(aarch64_autovec_preference) String(prefer-asimd) Value(AARCH64_AUTOVEC_PREFER_ASIMD)
+
+EnumValue
+Enum(aarch64_autovec_preference) String(prefer-sve) Value(AARCH64_AUTOVEC_PREFER_SVE)
 
 -param=aarch64-loop-vect-issue-rate-niters=
 Target Joined UInteger Var(aarch64_loop_vect_issue_rate_niters) Init(6) IntegerRange(0, 65536) Param
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 32b772d..1dede82 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -17175,22 +17175,20 @@ The precision of division is propotional to this param when division
 approximation is enabled.  The default value is 2.
 
 @item aarch64-autovec-preference
-Force an ISA selection strategy for auto-vectorization.  Accepts values from
-0 to 4, inclusive.
+Force an ISA selection strategy for auto-vectorization.
 @table @samp
-@item 0
+@item default
 Use the default heuristics.
-@item 1
+@item asimd-only
 Use only Advanced SIMD for auto-vectorization.
-@item 2
+@item sve-only
 Use only SVE for auto-vectorization.
-@item 3
+@item prefer-asimd
 Use both Advanced SIMD and SVE.  Prefer Advanced SIMD when the costs are
 deemed equal.
-@item 4
+@item prefer-sve
 Use both Advanced SIMD and SVE.  Prefer SVE when the costs are deemed equal.
 @end table
-The default value is 0.
 
 @item aarch64-ldp-policy
 Fine-grained policy for load pairs.
diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only.c
new file mode 100644
index 0000000..c983b26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_asimd-only.c
@@ -0,0 +1,4 @@
+/* { dg-options "--param aarch64-autovec-preference=asimd-only" } */
+
+void
+foo (void) {}
diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_default.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_default.c
new file mode 100644
index 0000000..d02acf1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_default.c
@@ -0,0 +1,4 @@
+/* { dg-options "--param aarch64-autovec-preference=default" } */
+
+void
+foo (void) {}
diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd.c
new file mode 100644
index 0000000..a40d7bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-asimd.c
@@ -0,0 +1,4 @@
+/* { dg-options "--param aarch64-autovec-preference=prefer-asimd" } */
+
+void
+foo (void) {}
diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve.c
new file mode 100644
index 0000000..b8b995f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_prefer-sve.c
@@ -0,0 +1,4 @@
+/* { dg-options "--param aarch64-autovec-preference=prefer-sve" } */
+
+void
+foo (void) {}
diff --git a/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only.c b/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only.c
new file mode 100644
index 0000000..f9c567f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/autovec_param_sve-only.c
@@ -0,0 +1,4 @@
+/* { dg-options "--param aarch64-autovec-preference=sve-only" } */
+
+void
+foo (void) {}
diff --git a/gcc/testsuite/gcc.target/aarch64/neoverse_v1_2.c b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_2.c
index 45d7e81..c95fd46 100644
--- a/gcc/testsuite/gcc.target/aarch64/neoverse_v1_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -mcpu=neoverse-v1 --param aarch64-autovec-preference=1 -fdump-tree-vect-details" } */
+/* { dg-options "-O2 -mcpu=neoverse-v1 --param aarch64-autovec-preference=asimd-only -fdump-tree-vect-details" } */
 
 void
 f (float x[restrict][100], float y[restrict][100])
diff --git a/gcc/testsuite/gcc.target/aarch64/neoverse_v1_3.c b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_3.c
index de31fc1..f5c9496 100644
--- a/gcc/testsuite/gcc.target/aarch64/neoverse_v1_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/neoverse_v1_3.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -mcpu=neoverse-v1 --param aarch64-autovec-preference=2 -fdump-tree-vect-details" } */
+/* { dg-options "-O2 -mcpu=neoverse-v1 --param aarch64-autovec-preference=sve-only -fdump-tree-vect-details" } */
 
 void
 f (float x[restrict][100], float y[restrict][100])
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c
index 96e9935..9e14bc6 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=2" } */
+/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=sve-only" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_4.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_4.c
index 6f969a8..cc2363c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=2" } */
+/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=sve-only" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_5.c
index e6ec515..078318e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_unary_5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=2" } */
+/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=sve-only" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c
index 7ed3592..0b09847 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=2" } */
+/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=256 --param=aarch64-autovec-preference=sve-only" } */
 
 #include <stdint.h>
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cond_xorsign_2.c b/gcc/testsuite/gcc.target/aarch64/sve/cond_xorsign_2.c
index 274dd0e..20ec970 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/cond_xorsign_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cond_xorsign_2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msve-vector-bits=128 --param aarch64-autovec-preference=2" } */
+/* { dg-options "-O2 -msve-vector-bits=128 --param aarch64-autovec-preference=sve-only" } */
 
 #include "cond_xorsign_1.c"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr98268-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr98268-1.c
index fdbe55e..9b16099 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pr98268-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr98268-1.c
@@ -1,5 +1,5 @@
 /* { dg-do link } */
-/* { dg-options "-flto -O -ftree-vectorize --param=aarch64-autovec-preference=3" } */
+/* { dg-options "-flto -O -ftree-vectorize --param=aarch64-autovec-preference=prefer-asimd" } */
 /* { dg-additional-sources "pr98268-2.c" } */
 
 short d, e;
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr98268-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr98268-2.c
index de3b05d..59cea96 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/pr98268-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr98268-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O -ftree-vectorize --param=aarch64-autovec-preference=3" } */
+/* { dg-options "-O -ftree-vectorize --param=aarch64-autovec-preference=prefer-asimd" } */
 
 extern short d[], e[];
 void f(char a, long *b) {