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authorRaphael Moreira Zinsly <rzinsly@ventanamicro.com>2024-09-05 22:14:32 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-09-05 22:14:32 -0600
commit1dd175a0ccdd0ff4e7cb6668164a4fe99e47015d (patch)
tree36a02136fc9e6da12d85ff2819bf83f51d63b668 /gcc
parentecdb9f59d0915f154a4c8fa56e11d81479f535eb (diff)
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[PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves
Changes since v1: - Fix synthesis-15.c. -- >8 -- Improve handling of constants where the high half can be constructed by inverting the lower half. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Detect constants were the higher half is the lower half inverted. gcc/testsuite/ChangeLog: * gcc.target/riscv/synthesis-15.c: New test.
Diffstat (limited to 'gcc')
-rw-r--r--gcc/config/riscv/riscv.cc30
-rw-r--r--gcc/testsuite/gcc.target/riscv/synthesis-15.c26
2 files changed, 56 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 064ffa4..6efe14f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1346,6 +1346,36 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value,
}
}
}
+
+ if (cost > 5 && !bit31)
+ {
+ /* For constants where the upper half is the lower half inverted we can flip
+ it with an xor and do a shift 32 followed by an or. */
+ if (hival == (~loval & 0xffffffff))
+ {
+ alt_cost = 3 + riscv_build_integer_1 (alt_codes,
+ sext_hwi (loval, 32), mode);
+ if (alt_cost < cost)
+ {
+ alt_codes[alt_cost - 4].save_temporary = true;
+ alt_codes[alt_cost - 3].code = XOR;
+ alt_codes[alt_cost - 3].value = -1;
+ alt_codes[alt_cost - 3].use_uw = false;
+ alt_codes[alt_cost - 3].save_temporary = false;
+ alt_codes[alt_cost - 2].code = ASHIFT;
+ alt_codes[alt_cost - 2].value = 32;
+ alt_codes[alt_cost - 2].use_uw = false;
+ alt_codes[alt_cost - 2].save_temporary = false;
+ alt_codes[alt_cost - 1].code = CONCAT;
+ alt_codes[alt_cost - 1].value = 0;
+ alt_codes[alt_cost - 1].use_uw = false;
+ alt_codes[alt_cost - 1].save_temporary = false;
+
+ memcpy (codes, alt_codes, sizeof (alt_codes));
+ cost = alt_cost;
+ }
+ }
+ }
}
return cost;
diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-15.c b/gcc/testsuite/gcc.target/riscv/synthesis-15.c
new file mode 100644
index 0000000..dc1f8b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/synthesis-15.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* We aggressively skip as we really just need to test the basic synthesis
+ which shouldn't vary based on the optimization level. -O1 seems to work
+ and eliminates the usual sources of extraneous dead code that would throw
+ off the counts. */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv64gc" } */
+
+/* Rather than test for a specific synthesis of all these constants or
+ having thousands of tests each testing one variant, we just test the
+ total number of instructions.
+
+ This isn't expected to change much and any change is worthy of a look. */
+/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori|or)" 60 } } */
+
+unsigned long foo_0xcafe605f35019fa0(void) { return 0xcafe605f35019fa0UL; }
+unsigned long foo_0x87a80d217857f2de(void) { return 0x87a80d217857f2deUL; }
+unsigned long foo_0x6699f19c19660e63(void) { return 0xe699f19c19660e63UL; }
+unsigned long foo_0xec80e48a137f1b75(void) { return 0xec80e48a137f1b75UL; }
+unsigned long foo_0xc7d7193e3828e6c1(void) { return 0xc7d7193e3828e6c1UL; }
+unsigned long foo_0xfc627816039d87e9(void) { return 0xfc627816039d87e9UL; }
+unsigned long foo_0xbd69e83e429617c1(void) { return 0xbd69e83e429617c1UL; }
+unsigned long foo_0xdbee7ee624118119(void) { return 0xdbee7ee624118119UL; }
+unsigned long foo_0xf3fe20820c01df7d(void) { return 0xf3fe20820c01df7dUL; }
+unsigned long foo_0x8f1dc29470e23d6b(void) { return 0x8f1dc29470e23d6bUL; }