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| author | GCC Administrator <gccadmin@gcc.gnu.org> | 2024-10-21 00:17:11 +0000 |
|---|---|---|
| committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2024-10-21 00:17:11 +0000 |
| commit | 0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853 (patch) | |
| tree | 49205b61821b29a2f524bcafbff7b18a0f7639b2 /gcc | |
| parent | 01f50ebfd97a7bd17a4cc94c403a8e126986c02c (diff) | |
| download | gcc-0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853.zip gcc-0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853.tar.gz gcc-0ceb5cc1867fce940b2f4eaaa2b6ace49cb0b853.tar.bz2 | |
Daily bump.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/DATESTAMP | 2 | ||||
| -rw-r--r-- | gcc/m2/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 10 |
4 files changed, 27 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3c2a7b7..6c55b4e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2024-10-20 Jeff Law <jlaw@ventanamicro.com> + + Revert: + 2024-10-19 Craig Blackmore <craig.blackmore@embecosm.com> + + * config/riscv/riscv.cc (riscv_use_by_pieces_infrastructure_p): + New function. + (TARGET_USE_BY_PIECES_INFRASTRUCTURE_P): Define. + 2024-10-19 Andrew Pinski <quic_apinski@quicinc.com> PR tree-optimization/112418 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f616e4b..18b2d48 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20241020 +20241021 diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 7f775ea..05b7d7c 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,10 @@ +2024-10-20 Gaius Mulley <gaiusmod2@gmail.com> + + * gm2-compiler/M2MetaError.mod (op): Corrected ordering. + * gm2-compiler/P2SymBuild.def: Remove comment. + * gm2-compiler/P2SymBuild.mod (GetComparison): Replace + the word less with fewer. + 2024-10-19 Gaius Mulley <gaiusmod2@gmail.com> * gm2-compiler/M2MetaError.mod (op): Alphabetically order diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 658829c..ebaa290 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2024-10-20 Jeff Law <jlaw@ventanamicro.com> + + Revert: + 2024-10-20 Craig Blackmore <craig.blackmore@embecosm.com> + + * gcc.target/riscv/rvv/autovec/pr113469.c: Expect mf2 setmem. + * gcc.target/riscv/rvv/base/setmem-2.c: Update f1 to expect + straight-line vector memset. + * gcc.target/riscv/rvv/base/setmem-3.c: Likewise. + 2024-10-19 Lewis Hyatt <lhyatt@gmail.com> PR preprocessor/114423 |