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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-03-13 22:17:57 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-03-17 17:48:58 +0800 |
| commit | 02880e7803b19c357718abd2f0d567b4a761f318 (patch) | |
| tree | 66bb93fb13eae23275ce755fe7998a811cd3d8ae /gcc | |
| parent | 2bb71424636fba7944b36b1689e9df22a53f1a3f (diff) | |
| download | gcc-02880e7803b19c357718abd2f0d567b4a761f318.zip gcc-02880e7803b19c357718abd2f0d567b4a761f318.tar.gz gcc-02880e7803b19c357718abd2f0d567b4a761f318.tar.bz2 | |
RISC-V: Use reg_or_subregno to check regno [PR109092]
gcc/ChangeLog:
PR target/109092
* config/riscv/riscv.md: Fix subreg bug.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/riscv/riscv.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 863400c..bc384d9 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1369,8 +1369,8 @@ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] "TARGET_64BIT && !TARGET_ZBA - && !(REG_P (operands[1]) - && REGNO (operands[1]) == VL_REGNUM)" + && !(register_operand (operands[1], SImode) + && reg_or_subregno (operands[1]) == VL_REGNUM)" "@ # lwu\t%0,%1" @@ -1752,7 +1752,7 @@ "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && !(register_operand (operands[1], SImode) - && REGNO (operands[1]) == VL_REGNUM)" + && reg_or_subregno (operands[1]) == VL_REGNUM)" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") (set_attr "mode" "SI") |