amdgcn: Remove TARGET_GCN3

The only GCN3 ISA device was remove (Fiji, gfx803) so all the GCN3-specific
code and features can be removed from the back-end.

gcc/ChangeLog:

	* config/gcn/gcn-opts.h (enum gcn_isa): Delete ISA_GCN3.
	(TARGET_GCN3): Delete.
	(TARGET_GCN3_PLUS): Delete.
	(TARGET_M0_LDS_LIMIT): Delete.
	* config/gcn/gcn-valu.md
	(gather<mode>_insn_1offset<exec>): Remove TARGET_GCN3 from conditions.
	(*<reduc_op>_dpp_shr_<mode>): Likewise.
	* config/gcn/gcn.cc (enum gcn_isa): Change default to ISA_GCN5.
	(gcn_expand_prologue): Remove TARGET_M0_LDS_LIMIT feature.
	(gcn_expand_reduc_scalar): Remove TARGET_GCN3 conditions.
	* config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Remove TARGET_GCN3.

4 files changed, 7 insertions, 31 deletions

diff --git a/gcc/config/gcn/gcn-opts.h b/gcc/config/gcn/gcn-opts.h
index a896a80..6f5969d 100644
--- a/gcc/config/gcn/gcn-opts.h
+++ b/gcc/config/gcn/gcn-opts.h
@@ -44,7 +44,6 @@ enum processor_type
 /* Set in gcn_option_override.  */
 extern enum gcn_isa {
   ISA_UNKNOWN,
-  ISA_GCN3,
   ISA_GCN5,
   ISA_RDNA2,
   ISA_RDNA3,
@@ -52,8 +51,6 @@ extern enum gcn_isa {
   ISA_CDNA2
 } gcn_isa;
 
-#define TARGET_GCN3 (gcn_isa == ISA_GCN3)
-#define TARGET_GCN3_PLUS (gcn_isa >= ISA_GCN3)
 #define TARGET_GCN5 (gcn_isa == ISA_GCN5)
 #define TARGET_GCN5_PLUS (gcn_isa >= ISA_GCN5)
 #define TARGET_CDNA1 (gcn_isa == ISA_CDNA1)
@@ -65,7 +62,6 @@ extern enum gcn_isa {
 #define TARGET_RDNA3 (gcn_isa == ISA_RDNA3)
 
 
-#define TARGET_M0_LDS_LIMIT (TARGET_GCN3)
 #define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS || TARGET_RDNA3)
 
 #define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF)
@@ -92,8 +88,6 @@ enum hsaco_attr_type
 #define TARGET_11BIT_GLOBAL_OFFSET TARGET_RDNA2_PLUS
 /* The work item details are all encoded into v0.  */
 //#define TARGET_PACKED_WORK_ITEMS TARGET_PACKED_WORK_ITEMS
-/* m0 must be initialized in order to use LDS.  */
-//#define TARGET_M0_LDS_LIMIT TARGET_M0_LDS_LIMIT
 /* CDNA2 load/store costs are reduced.
  * TODO: what does this mean?  */
 #define TARGET_CDNA2_MEM_COSTS TARGET_CDNA2_PLUS
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index b24cf9b..54f4b14 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1156,10 +1156,9 @@
 	   (mem:BLK (scratch))]
 	  UNSPEC_GATHER))]
   "(AS_FLAT_P (INTVAL (operands[3]))
-    && ((TARGET_GCN3 && INTVAL(operands[2]) == 0)
-	|| ((unsigned HOST_WIDE_INT)INTVAL(operands[2]) < 0x1000)))
-    || (AS_GLOBAL_P (INTVAL (operands[3]))
-	&& (((unsigned HOST_WIDE_INT)INTVAL(operands[2]) + 0x1000) < 0x2000))"
+    && ((unsigned HOST_WIDE_INT)INTVAL(operands[2]) < 0x1000))
+   || (AS_GLOBAL_P (INTVAL (operands[3]))
+       && (((unsigned HOST_WIDE_INT)INTVAL(operands[2]) + 0x1000) < 0x2000))"
   {
     addr_space_t as = INTVAL (operands[3]);
     const char *glc = INTVAL (operands[4]) ? " glc" : "";
@@ -4297,10 +4296,7 @@
 	   (match_operand:V_1REG 2 "register_operand" "v")
 	   (match_operand:SI 3 "const_int_operand"        "n")]
 	  REDUC_UNSPEC))]
-  ; GCN3 requires a carry out, GCN5 not
-  "!(TARGET_GCN3 && SCALAR_INT_MODE_P (<SCALAR_MODE>mode)
-     && <reduc_unspec> == UNSPEC_PLUS_DPP_SHR)
-   && TARGET_DPP_FULL"
+  "TARGET_DPP_FULL"
   {
     return gcn_expand_dpp_shr_insn (<MODE>mode, "<reduc_insn>",
 				    <reduc_unspec>, INTVAL (operands[3]));
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc
index 89aab6f..fd2b860 100644
--- a/gcc/config/gcn/gcn.cc
+++ b/gcc/config/gcn/gcn.cc
@@ -68,7 +68,7 @@ static bool ext_gcn_constants_init = 0;
 
 /* Holds the ISA variant, derived from the command line parameters.  */
 
-enum gcn_isa gcn_isa = ISA_GCN3;	/* Default to GCN3.  */
+enum gcn_isa gcn_isa = ISA_GCN5;	/* Default to GCN5.  */
 
 /* Reserve this much space for LDS (for propagating variables from
    worker-single mode to worker-partitioned mode), per workgroup.  Global
@@ -3556,17 +3556,6 @@ gcn_expand_prologue ()
   /* Ensure that the scheduler doesn't do anything unexpected.  */
   emit_insn (gen_blockage ());
 
-  if (TARGET_M0_LDS_LIMIT)
-  {
-    /* m0 is initialized for the usual LDS DS and FLAT memory case.
-       The low-part is the address of the topmost addressable byte, which is
-       size-1.  The high-part is an offset and should be zero.  */
-    emit_move_insn (gen_rtx_REG (SImode, M0_REG),
-	gen_int_mode (LDS_SIZE, SImode));
-
-    emit_insn (gen_prologue_use (gen_rtx_REG (SImode, M0_REG)));
-  }
-
   if (cfun && cfun->machine && !cfun->machine->normal_function && flag_openmp)
     {
       /* OpenMP kernels have an implicit call to gomp_gcn_enter_kernel.  */
@@ -5591,8 +5580,7 @@ gcn_expand_reduc_scalar (machine_mode mode, rtx src, int unspec)
 		    || unspec == UNSPEC_UMAX_DPP_SHR);
   bool use_plus_carry = unspec == UNSPEC_PLUS_DPP_SHR
 			&& GET_MODE_CLASS (mode) == MODE_VECTOR_INT
-			/* FIXME: why GCN3?  */
-			&& (TARGET_GCN3 || scalar_mode == DImode);
+			&& scalar_mode == DImode;
 
   if (use_plus_carry)
     unspec = UNSPEC_PLUS_CARRY_DPP_SHR;
diff --git a/gcc/config/gcn/gcn.h b/gcc/config/gcn/gcn.h
index a48fdc8..70bece7 100644
--- a/gcc/config/gcn/gcn.h
+++ b/gcc/config/gcn/gcn.h
@@ -20,9 +20,7 @@
   do                                                                           \
     {                                                                          \
       builtin_define ("__AMDGCN__");                                           \
-      if (TARGET_GCN3)                                                         \
-	builtin_define ("__GCN3__");                                           \
-      else if (TARGET_GCN5)                                                    \
+      if (TARGET_GCN5)                                                    \
 	builtin_define ("__GCN5__");                                           \
       else if (TARGET_CDNA1)                                                   \
 	builtin_define ("__CDNA1__");                                          \