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authorWilco Dijkstra <wdijkstr@arm.com>2018-11-14 12:35:36 +0000
committerWilco Dijkstra <wilco@gcc.gnu.org>2018-11-14 12:35:36 +0000
commitff4d8480403be6ab92e07f6981e7bfc04c3863c9 (patch)
tree558da2565d60de053556689fc74e2fb15ff65e03 /gcc
parentb258173580ec8ed49c1655593531c9819e064730 (diff)
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[AArch64] Fix PR62178 testcase failures
The testcase for PR62178 has been failing for a while due to the pass conditions being too tight, resulting in failures with -mcmodel=tiny: ldr q2, [x0], 124 ld1r {v1.4s}, [x1], 4 cmp x0, x2 mla v0.4s, v2.4s, v1.4s bne .L7 -mcmodel=small generates the slightly different: ldr q1, [x0], 124 ldr s2, [x1, 4]! cmp x0, x2 mla v0.4s, v1.4s, v2.s[0] bne .L7 This is due to Combine merging a DUP instruction with either a load or MLA - we can't force it to prefer one over the other. However the generated vector loop is fast either way since it generates MLA and merges the DUP either with a load or MLA. So relax the conditions slightly and check we still generate MLA and there is no DUP or FMOV. The testcase now passes - committed as obvious. testsuite/ * gcc.target/aarch64/pr62178.c: Relax scan-assembler checks. From-SVN: r266139
Diffstat (limited to 'gcc')
-rw-r--r--gcc/testsuite/ChangeLog4
-rw-r--r--gcc/testsuite/gcc.target/aarch64/pr62178.c5
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f8bb63f..303bca4 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-11-14 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * gcc.target/aarch64/pr62178.c: Relax scan-assembler checks.
+
2018-11-14 Patrick Bernardi <bernardi@adacore.com>
* gnat.dg/rt_signals.adb: New testcase.
diff --git a/gcc/testsuite/gcc.target/aarch64/pr62178.c b/gcc/testsuite/gcc.target/aarch64/pr62178.c
index ccb400f..f50567e 100644
--- a/gcc/testsuite/gcc.target/aarch64/pr62178.c
+++ b/gcc/testsuite/gcc.target/aarch64/pr62178.c
@@ -16,6 +16,7 @@ void foo (void) {
}
}
-/* { dg-final { scan-assembler "ldr\\ts\[0-9\]+, \\\[x\[0-9\]+, \[0-9\]+\\\]!" } } */
/* { dg-final { scan-assembler "ldr\\tq\[0-9\]+, \\\[x\[0-9\]+\\\], \[0-9\]+" } } */
-/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[0\\\]" } } */
+/* { dg-final { scan-assembler "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+" } } */
+/* { dg-final { scan-assembler-not { dup } } } */
+/* { dg-final { scan-assembler-not { fmov } } } */