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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-03-03 23:16:13 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-03-25 21:04:23 +0000 |
| commit | fe4b53b2e7e58d3bcf476a0a319b51a5a8c668a2 (patch) | |
| tree | 9d4ad99210e583ff48d7a4645e83b4a10b63f956 /gcc | |
| parent | 48817fbd7616f086ac7bb1dd38b862f78762c9b8 (diff) | |
| download | gcc-fe4b53b2e7e58d3bcf476a0a319b51a5a8c668a2.zip gcc-fe4b53b2e7e58d3bcf476a0a319b51a5a8c668a2.tar.gz gcc-fe4b53b2e7e58d3bcf476a0a319b51a5a8c668a2.tar.bz2 | |
testsuite: adjustments for amdgcn
2020-03-25 Andrew Stubbs <ams@codesourcery.com>
gcc/testsuite/
* gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn.
* lib/target-supports.exp (check_effective_target_vect_unpack):
Add amdgcn.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 5 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 3 |
3 files changed, 11 insertions, 3 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fe8460c..e750dcb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-25 Andrew Stubbs <ams@codesourcery.com> + + * gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn. + * lib/target-supports.exp (check_effective_target_vect_unpack): + Add amdgcn. + 2020-03-25 Jakub Jelinek <jakub@redhat.com> PR target/94292 diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index 813b1af..fe52d18 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -19,5 +19,6 @@ void foo(unsigned *p1, unsigned short *p2) /* Disable for SVE because for long or variable-length vectors we don't get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, - because there we can vectorize the epilogue using mixed vector sizes. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64*-*-* } } } } */ + because there we can vectorize the epilogue using mixed vector sizes. + Likewise for AMD GCN. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 10353af..3654e7b 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6717,7 +6717,8 @@ proc check_effective_target_vect_unpack { } { || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok] && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || [istarget amdgcn*-*-*] }}] } # Return 1 if the target plus current options does not guarantee |