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| author | Bernd Edlinger <bernd.edlinger@hotmail.de> | 2017-09-06 07:47:52 +0000 |
|---|---|---|
| committer | Bernd Edlinger <edlinger@gcc.gnu.org> | 2017-09-06 07:47:52 +0000 |
| commit | fb117b1c9139a31068b31417d7a65d0cdc9448ec (patch) | |
| tree | 56a13a2e0c8410ad58d782c15278134ed9a77dbc /gcc | |
| parent | 5aa102aa78e6256fabae6beca698d533e27348ff (diff) | |
| download | gcc-fb117b1c9139a31068b31417d7a65d0cdc9448ec.zip gcc-fb117b1c9139a31068b31417d7a65d0cdc9448ec.tar.gz gcc-fb117b1c9139a31068b31417d7a65d0cdc9448ec.tar.bz2 | |
re PR target/77308 (surprisingly large stack usage for sha512 on arm)
2017-09-06 Bernd Edlinger <bernd.edlinger@hotmail.de>
PR target/77308
* config/arm/predicates.md (arm_general_adddi_operand): Create new
non-vfp predicate.
* config/arm/arm.md (*arm_adddi3, *arm_subdi3): Use new predicates.
From-SVN: r251752
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 15 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 5 |
3 files changed, 19 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1b3bddb..0922d66 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-09-06 Bernd Edlinger <bernd.edlinger@hotmail.de> + + PR target/77308 + * config/arm/predicates.md (arm_general_adddi_operand): Create new + non-vfp predicate. + * config/arm/arm.md (*arm_adddi3, *arm_subdi3): Use new predicates. + 2017-09-05 Jeff Law <law@redhat.com> PR tree-optimization/64910 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 064c98c..df73e73 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -457,14 +457,13 @@ ) (define_insn_and_split "*arm_adddi3" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r,&r,&r") - (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0, r, 0, r") - (match_operand:DI 2 "arm_adddi_operand" "r, 0, r, Dd, Dd"))) + [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r,&r,&r") + (plus:DI (match_operand:DI 1 "arm_general_register_operand" "%0, 0, r, 0, r") + (match_operand:DI 2 "arm_general_adddi_operand" "r, 0, r, Dd, Dd"))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && !TARGET_NEON" "#" - "TARGET_32BIT && ((!TARGET_NEON && !TARGET_IWMMXT) || reload_completed) - && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))" + "TARGET_32BIT && ((!TARGET_NEON && !TARGET_IWMMXT) || reload_completed)" [(parallel [(set (reg:CC_C CC_REGNUM) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) @@ -1263,9 +1262,9 @@ ) (define_insn_and_split "*arm_subdi3" - [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r") - (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") - (match_operand:DI 2 "s_register_operand" "r,0,0"))) + [(set (match_operand:DI 0 "arm_general_register_operand" "=&r,&r,&r") + (minus:DI (match_operand:DI 1 "arm_general_register_operand" "0,r,0") + (match_operand:DI 2 "arm_general_register_operand" "r,0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && !TARGET_NEON" "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 3e25cd1..e24877e 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -82,6 +82,11 @@ || REGNO (op) >= FIRST_PSEUDO_REGISTER)); }) +(define_predicate "arm_general_adddi_operand" + (ior (match_operand 0 "arm_general_register_operand") + (and (match_code "const_int") + (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)")))) + (define_predicate "vfp_register_operand" (match_code "reg,subreg") { |