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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-03-08 17:29:02 +0000 |
|---|---|---|
| committer | Andre Vieira <avieira@gcc.gnu.org> | 2019-03-08 17:29:02 +0000 |
| commit | f65112f61661d4a62b8952eda126e4cbca4195b1 (patch) | |
| tree | 886eb00f3274962305c3c1290189a45c573d4a67 /gcc | |
| parent | 9a53d503a433b3ca0c4e312e9ebea5f1b344efed (diff) | |
| download | gcc-f65112f61661d4a62b8952eda126e4cbca4195b1.zip gcc-f65112f61661d4a62b8952eda126e4cbca4195b1.tar.gz gcc-f65112f61661d4a62b8952eda126e4cbca4195b1.tar.bz2 | |
[GCC, Arm] Fix availability of FP16-FP64 conversion instructions
vcvtb.f16.f64 and vcvtb.f64.f16 were being made available even for FPUs that do
not support double precision. This patch fixes that.
gcc/ChangeLog:
2019-03-08 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.h (TARGET_FP16_TO_DOUBLE): Add TARGET_VFP_DOUBLE
requirement.
gcc/testsuite/ChangeLog:
2019-03-08 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/f16_f64_conv_no_dp.c: New test.
From-SVN: r269499
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/f16_f64_conv_no_dp.c | 15 |
4 files changed, 25 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ecc07d..ad486b4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-03-08 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * config/arm/arm.h (TARGET_FP16_TO_DOUBLE): Add TARGET_VFP_DOUBLE + requirement. + 2019-03-08 Uroš Bizjak <ubizjak@gmail.com> PR target/68924 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 103d390..7adafea 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -195,7 +195,7 @@ extern tree arm_fp16_type_node; /* FPU supports converting between HFmode and DFmode in a single hardware step. */ #define TARGET_FP16_TO_DOUBLE \ - (TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5)) + (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) /* FPU supports fused-multiply-add operations. */ #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a58b29d..13b91c7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-03-08 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * gcc.target/arm/f16_f64_conv_no_dp.c: New test. + 2019-03-08 Uroš Bizjak <ubizjak@gmail.com> PR target/68924 diff --git a/gcc/testsuite/gcc.target/arm/f16_f64_conv_no_dp.c b/gcc/testsuite/gcc.target/arm/f16_f64_conv_no_dp.c new file mode 100644 index 0000000..99b62a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/f16_f64_conv_no_dp.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-skip-if "do not override fpu" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv5-sp-d16" } } */ +/* { dg-skip-if "do not disable fpu" { *-*-* } { "-mfloat-abi=soft" } { * } } */ +/* { dg-skip-if "do not override fp16-format" { *-*-* } { "-mfp16-format=*" } { "-mfp16-format=ieee" } } */ +/* { dg-options "-O1 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mfp16-format=ieee" } */ + +__fp16 foo (double a) +{ + return a; +} + +double bar (__fp16 a) +{ + return a; +} |