diff options
| author | Aldy Hernandez <aldyh@redhat.com> | 2003-05-05 17:40:03 +0000 |
|---|---|---|
| committer | Aldy Hernandez <aldyh@gcc.gnu.org> | 2003-05-05 17:40:03 +0000 |
| commit | f5119d10faca5f15af8293286b518ef342817629 (patch) | |
| tree | 4eb3838ca27b6d84e27d860075cb5aebbca4dcba /gcc | |
| parent | 25ecd459a1d04c0a7b47d7d65f1ee0fd5f102ea7 (diff) | |
| download | gcc-f5119d10faca5f15af8293286b518ef342817629.zip gcc-f5119d10faca5f15af8293286b518ef342817629.tar.gz gcc-f5119d10faca5f15af8293286b518ef342817629.tar.bz2 | |
rs6000.c (rs6000_expand_binop_builtin): Add evsubifw to builtins accepting 5-bit unsigned constants.
2003-05-05 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add
evsubifw to builtins accepting 5-bit unsigned constants.
(easy_vector_constant): Return if V1DImode. Fix typo.
[[Split portion of a mixed commit.]]
From-SVN: r66490.2
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 6 |
2 files changed, 11 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4477e0f..84bd445 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2003-05-05 Aldy Hernandez <aldyh@redhat.com> + * config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add + evsubifw to builtins accepting 5-bit unsigned constants. + (easy_vector_constant): Return if V1DImode. Fix typo. + +2003-05-05 Aldy Hernandez <aldyh@redhat.com> + * config/rs6000/spe.h: Revert licensing change from last patch. 2003-05-05 DJ Delorie <dj@redhat.com> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b5faabd..2f28301 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1510,6 +1510,9 @@ easy_vector_constant (op, mode) if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) return 0; + if (TARGET_SPE && mode == V1DImode) + return 0; + cst = INTVAL (CONST_VECTOR_ELT (op, 0)); cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); @@ -1524,7 +1527,7 @@ easy_vector_constant (op, mode) have the e500 timing specs. */ if (TARGET_SPE && mode == V2SImode && cst >= -0x7fff && cst <= 0x7fff - && cst2 >= -0x7fff && cst <= 0x7fff) + && cst2 >= -0x7fff && cst2 <= 0x7fff) return 1; if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode)) @@ -4721,6 +4724,7 @@ rs6000_expand_binop_builtin (icode, arglist, target) || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis + || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu) { /* Only allow 5-bit unsigned literals. */ |