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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-04-29 10:13:36 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-04-29 10:13:36 +0000 |
| commit | ee9da432b6cb3df2ba026dc66aa8a41b99512db5 (patch) | |
| tree | c390e55f20b39a2e86f12d2eb6e36ed3b0a58660 /gcc | |
| parent | 32966af8aaa84384baa4c1eb66b5efdd52055201 (diff) | |
| download | gcc-ee9da432b6cb3df2ba026dc66aa8a41b99512db5.zip gcc-ee9da432b6cb3df2ba026dc66aa8a41b99512db5.tar.gz gcc-ee9da432b6cb3df2ba026dc66aa8a41b99512db5.tar.bz2 | |
[ARM]Remove vec_shr and vec_shr optabs
* config/arm/neon.md (vec_shl<mode>, vec_shr<mode>): Remove.
From-SVN: r222568
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 65 |
2 files changed, 4 insertions, 65 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1e05574..9afd56e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2015-04-29 Alan Lawrence <alan.lawrence@arm.com> + + * config/arm/neon.md (vec_shl<mode>, vec_shr<mode>): Remove. + 2015-04-29 Tom de Vries <tom@codesourcery.com> PR tree-optimization/65893 diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index a48c39b..654d9d5 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1194,71 +1194,6 @@ [(set_attr "type" "neon_add_widen")] ) -;; VEXT can be used to synthesize coarse whole-vector shifts with 8-bit -;; shift-count granularity. That's good enough for the middle-end's current -;; needs. - -;; Note that it's not safe to perform such an operation in big-endian mode, -;; due to element-ordering issues. - -(define_expand "vec_shr_<mode>" - [(match_operand:VDQ 0 "s_register_operand" "") - (match_operand:VDQ 1 "s_register_operand" "") - (match_operand:SI 2 "const_multiple_of_8_operand" "")] - "TARGET_NEON && !BYTES_BIG_ENDIAN" -{ - rtx zero_reg; - HOST_WIDE_INT num_bits = INTVAL (operands[2]); - const int width = GET_MODE_BITSIZE (<MODE>mode); - const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; - rtx (*gen_ext) (rtx, rtx, rtx, rtx) = - (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; - - if (num_bits == width) - { - emit_move_insn (operands[0], operands[1]); - DONE; - } - - zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); - operands[0] = gen_lowpart (bvecmode, operands[0]); - operands[1] = gen_lowpart (bvecmode, operands[1]); - - emit_insn (gen_ext (operands[0], operands[1], zero_reg, - GEN_INT (num_bits / BITS_PER_UNIT))); - DONE; -}) - -(define_expand "vec_shl_<mode>" - [(match_operand:VDQ 0 "s_register_operand" "") - (match_operand:VDQ 1 "s_register_operand" "") - (match_operand:SI 2 "const_multiple_of_8_operand" "")] - "TARGET_NEON && !BYTES_BIG_ENDIAN" -{ - rtx zero_reg; - HOST_WIDE_INT num_bits = INTVAL (operands[2]); - const int width = GET_MODE_BITSIZE (<MODE>mode); - const machine_mode bvecmode = (width == 128) ? V16QImode : V8QImode; - rtx (*gen_ext) (rtx, rtx, rtx, rtx) = - (width == 128) ? gen_neon_vextv16qi : gen_neon_vextv8qi; - - if (num_bits == 0) - { - emit_move_insn (operands[0], CONST0_RTX (<MODE>mode)); - DONE; - } - - num_bits = width - num_bits; - - zero_reg = force_reg (bvecmode, CONST0_RTX (bvecmode)); - operands[0] = gen_lowpart (bvecmode, operands[0]); - operands[1] = gen_lowpart (bvecmode, operands[1]); - - emit_insn (gen_ext (operands[0], zero_reg, operands[1], - GEN_INT (num_bits / BITS_PER_UNIT))); - DONE; -}) - ;; Helpers for quad-word reduction operations ; Add (or smin, smax...) the low N/2 elements of the N-element vector |