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| author | Joel Hutton <joel.hutton@arm.com> | 2020-11-19 10:28:38 +0000 |
|---|---|---|
| committer | Joel Hutton <joel.hutton@arm.com> | 2020-11-19 11:47:43 +0000 |
| commit | ec46904edfec162f32b8b411301374afc8f5fcb5 (patch) | |
| tree | cde918f2fcb2d7f08459b35602ca54297f71bbd9 /gcc | |
| parent | ec383f0bdb4077b744d493d02afff5f13f33029e (diff) | |
| download | gcc-ec46904edfec162f32b8b411301374afc8f5fcb5.zip gcc-ec46904edfec162f32b8b411301374afc8f5fcb5.tar.gz gcc-ec46904edfec162f32b8b411301374afc8f5fcb5.tar.bz2 | |
[1/3][aarch64] Add vec_widen patterns to aarch64
Add widening add and subtract patterns to the aarch64
backend. These allow taking vectors of N elements of size S
and performing and add/subtract on the high or low half
widening the resulting elements and storing N/2 elements of size 2*S.
These correspond to the addl,addl2,subl,subl2 instructions.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md: New patterns
vec_widen_saddl_lo/hi_<mode>.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 2cf6fe9..e8c951f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3382,6 +3382,53 @@ [(set_attr "type" "neon_<ADDSUB:optab>_long")] ) +(define_expand "vec_widen_<su>addl_lo_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + emit_insn (gen_aarch64_<su>addl<mode>_lo_internal (operands[0], operands[1], + operands[2], p)); + DONE; +}) + +(define_expand "vec_widen_<su>addl_hi_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>addl<mode>_hi_internal (operands[0], operands[1], + operands[2], p)); + DONE; +}) + +(define_expand "vec_widen_<su>subl_lo_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + emit_insn (gen_aarch64_<su>subl<mode>_lo_internal (operands[0], operands[1], + operands[2], p)); + DONE; +}) + +(define_expand "vec_widen_<su>subl_hi_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" +{ + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>subl<mode>_hi_internal (operands[0], operands[1], + operands[2], p)); + DONE; +}) (define_expand "aarch64_saddl2<mode>" [(match_operand:<VWIDE> 0 "register_operand") |