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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:23:11 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:23:11 -0700 |
| commit | ea25b8487030ad75dedbbffdbb0836a3b637e74c (patch) | |
| tree | 1a88a668e8c0e8e40c14a6f04d9ab80bf8203313 /gcc | |
| parent | 2da47f31e33b13e528006be0ae2287e7f470962f (diff) | |
| download | gcc-ea25b8487030ad75dedbbffdbb0836a3b637e74c.zip gcc-ea25b8487030ad75dedbbffdbb0836a3b637e74c.tar.gz gcc-ea25b8487030ad75dedbbffdbb0836a3b637e74c.tar.bz2 | |
i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE
Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3):
Changed to define_insn_and_split to support SSE emulation.
From-SVN: r271242
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 34 |
2 files changed, 32 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c086171..80b83cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,12 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>dv2si3): + Changed to define_insn_and_split to support SSE emulation. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3): Changed to define_insn_and_split to support SSE emulation. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index bcdd8f9..0a0b8a4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15814,26 +15814,44 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "ssse3_ph<plusminus_mnemonic>dv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") +(define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (vec_concat:V2SI (plusminus:SI (vec_select:SI - (match_operand:V2SI 1 "register_operand" "0") + (match_operand:V2SI 1 "register_operand" "0,0,Yv") (parallel [(const_int 0)])) (vec_select:SI (match_dup 1) (parallel [(const_int 1)]))) (plusminus:SI (vec_select:SI - (match_operand:V2SI 2 "nonimmediate_operand" "ym") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0)])) (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))] - "TARGET_SSSE3" - "ph<plusminus_mnemonic>d\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + ph<plusminus_mnemonic>d\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] +{ + /* Generate SSE version of the operation. */ + rtx op0 = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V4SImode, operands[1], + GET_MODE (operands[1])); + rtx op2 = lowpart_subreg (V4SImode, operands[2], + GET_MODE (operands[2])); + emit_insn (gen_ssse3_ph<plusminus_mnemonic>dv4si3 (op0, op1, op2)); + ix86_move_vector_high_sse_to_mmx (op0); + DONE; +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseiadd") (set_attr "atom_unit" "complex") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "avx2_pmaddubsw256" [(set (match_operand:V16HI 0 "register_operand" "=x,v") |